 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MC68HC05L16 MC68HC705L16 Data Sheet M68HC05 Microcontrollers MC68HC05L16 Rev. 4.1 9/2005 freescale.com Blank MC68HC05L16 MC68HC705L16 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date May, 2002 September, 2005 Revision Level 4.0 4.1 Description Reformatted to add additional page references and correct World Wide Web address Updated to meet Freescale identity guidelines. Page Number(s) N/A Throughout FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. (c) Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 3 Revision History MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 4 Freescale Semiconductor List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 3 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Chapter 6 Parallel Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 7 Oscillators/Clock Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Chapter 8 Simple Serial Peripheral Interface (SSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Chapter 9 Timer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Chapter 10 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Chapter 11 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Chapter 12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 13 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Chapter 14 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Appendix A MC68HC705L16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 5 List of Chapters MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2.1 Crystal or Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 XOSC1 and XOSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3.1 Crystal Resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.5 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.6 Port B (PB0-PB7/KWI0-KWI7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.7 Port C (PC0/SDI, PC1/SDO, PC2/SCK, PC3/TCAP, PC4/EVI, PC5/EVO, PC6/IRQ2, and PC7/IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.8 Port D (PD1-PD3/BP1-BP3 and PD4-PD7/FP34-FP27). . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.9 Port E (PE0-PE7/FP38-FP35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.10 VLCD1, VLCD2, and VLCD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.11 NDLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 Mode Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 Single-Chip Mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.3 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 15 15 17 17 17 18 18 18 19 19 19 19 19 19 20 20 20 20 20 21 21 Chapter 2 Memory Map 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read/Write Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of Internal Registers and I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 24 24 24 24 24 25 25 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 7 Table of Contents 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.5 2.6 2.7 Option Map for I/O Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistor Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistor Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open-Drain Output Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open-Drain Output Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Wakeup Input Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Check ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 31 31 32 32 33 33 34 34 34 Chapter 3 Central Processor Unit (CPU) 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 36 36 36 37 37 37 Chapter 4 Resets and Interrupts 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.3 4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ1 and IRQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Wakeup Interrupt (KWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ (KWI) Software Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 1 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSPI Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timebase Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 40 40 40 40 41 41 41 41 45 46 Chapter 5 Low-Power Modes 5.1 5.2 5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 8 Freescale Semiconductor Table of Contents Chapter 6 Parallel Input/Output (I/O) 6.1 6.2 6.2.1 6.2.2 6.3 6.4 6.4.1 6.4.2 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Direction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D MUX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E MUX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 52 52 52 53 53 54 55 55 56 56 56 57 57 Chapter 7 Oscillators/Clock Distributions 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 OSC Clock Divider and POR Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 System Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 OSC and XOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 OSC on Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 XOSC on Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2.1 XOSC with FOSCE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2.2 XOSC with FOSCE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2.3 XOSC with FOSCE = 0 and STOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2.4 Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 LCDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 STUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.3 TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.4 COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.5 Timebase Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.6 Timebase Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.7 Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 60 60 60 61 61 62 62 62 63 63 63 63 64 65 66 67 Chapter 8 Simple Serial Peripheral Interface (SSPI) 8.1 8.2 8.3 8.4 8.4.1 8.4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 69 69 70 71 71 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 9 Table of Contents 8.4.3 8.4.4 8.4.5 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.6.3 8.7 SPCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSPI Data I/O (SDI and SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 71 71 71 72 73 73 74 75 75 Chapter 9 Timer System 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Compare Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter Register 2 ............................................... Timebase Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Input 2 (EVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Output (EVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 79 79 80 80 81 82 82 82 85 87 87 88 88 89 91 93 Chapter 10 LCD Driver 10.1 10.2 10.3 10.4 10.5 10.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LCD Waveform Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Backplane Driver and Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Frontplane Driver and Port Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LCD Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LCD Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 10 Freescale Semiconductor Table of Contents Chapter 11 Instruction Set 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.4 11.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 103 103 103 103 104 104 104 104 104 105 105 106 107 108 108 109 114 Chapter 12 Electrical Specifications 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 118 118 118 119 120 121 122 Chapter 13 Mechanical Specifications 13.1 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Quad Flat Pack (QFP) -- Case 841B-01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 14 Ordering Information 14.1 14.2 14.3 14.4 14.5 14.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Ordering Forms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Program Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM Verification Units (RVUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 11 127 127 127 128 128 129 Table of Contents Appendix A MC68HC705L16 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.7.1 A.7.2 A.7.3 A.8 A.9 A.10 A.10.1 A.10.2 A.11 A.12 A.12.1 A.12.2 A.12.3 A.13 A.13.1 A.13.2 A.13.3 A.13.4 A.14 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differences between MC68HC05L16 and MC68HC705L16 . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Voltage (VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Chip Mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD 1/2 Duty and 1/2 Bias Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM Programming Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-Volt and 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 131 131 131 133 133 135 135 135 136 136 137 137 137 138 139 140 140 141 141 141 141 142 143 144 144 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 12 Freescale Semiconductor Chapter 1 General Description 1.1 Introduction The MC68HC05L16 is an 80-pin microcontroller unit (MCU) with highly sophisticated on-chip peripheral functions. The memory map includes 16 Kbytes of user ROM and 512 bytes of RAM. The MCU has five parallel ports: A, B, C, D, and E. The MC68HC05L16 includes a timebase circuit, 8- and 16-bit timers, a computer operating properly (COP) watchdog timer, liquid crystal display (LCD) drivers, and a simple serial peripheral interface (SSPI). 1.2 Features Features of the MC68HC05L16 MCU include: * Low-cost HC05 core * 16,400 Bytes of mask ROM, including 16 bytes of user vectors and 512 bytes of on-chip RAM * 16 bidirectional input-output (I/O) lines * Eight input-only lines * 15 output-only lines, including 8-bit key wakeup interrupts * Pullup resistors options * Open-drain outputs options * Two interrupt request (IRQ) inputs * 16-bit timer with input capture and output compare (timer 1) * 8-bit event counter/modulus clock divider (timer 2) * Simple serial peripheral interface (SSPI) * LCD drivers -- 1-to-4 backplane drivers x 27-to-39 frontplane drivers * On-chip timebase circuits with COP watchdog timer and timebase interrupts * Dual oscillators and selectable system clock frequency * Power-saving stop mode and wait mode * 80-pin quad flat pack (QFP) 1.3 MCU Structure Figure 1-1 shows the structure of the MC68HC05L16 MCU. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 13 General Description OSC1 OSC2 XOSC1 XOSC2 OSC DIV SEL XOSC DATA A DIR REG 2 INTERNAL PROCESSOR CLOCK TIMEBASE SYSTEM PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 KEY WAKEUP DATA B DIR REG PORT B PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 SRAM 512 BYTES SPI SELF-CHECK ROM 496 BYTES COP SYSTEM PORT A MASK ROM 16,384 BYTES + 16 BYTES PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6*/IRQ2 PC7*/IRQ1 DATA C DIR REG LCD RESET CPU CONTROL M68HC05 CPU ALU V DD V SS CPU REGISTERS ACCUMULATOR INDEX REGISTER TIMER2 PORT C FP0-PF26 DRIVERS FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 BP3/PD3 BP2/PD2 BP1/PD1 BP0 NDLY** PROGRAM COUNTER CONDITION CODE REG VLCD3 VLCD2 VLCD1 * Open Drain Only when Output ** The NDLY pin should be connected to VDD. Figure 1-1. Block Diagram NOTE A line over a signal name indicates an active low signal. For example, RESET is active low. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 14 Freescale Semiconductor PORT D PORT E STACK POINTER Mask Options 1.4 Mask Options The three mask options on the MC68HC05L16 are: 1. RSTR: RESET pin pullup resistor 2. OSCR: OSC feedback resistor 3. XOSCR: XOSC feedback/damping resistor See 2.4.6 Mask Option Status Register. 1.5 Functional Pin Description The MC68HC05L16 is available in the 80-pin QFP. The pin assignment is shown in Figure 1-2. 80 VDD FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 VLCD3 VLCD2 VLCD1 VSS NDLY** XOSC1 XOSC2 RESET 1 FP27/PE7 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 61 60 VSS FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1/PD1 BP2/PD2 BP3/PD3 VDD PC7*/IRQ1 PC6*/IRQ2 PC5/EVO PC4/EVI PC3/TCAP PC2/SCK 20 21 40 41 * Open Drain Only when Output ** The NDLY pin should be connected to VDD. Figure 1-2. Pin Assignment for Single-Chip Mode MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 15 OSC1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO General Description Table 1-1. Pin Configuration Pin Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 17 47 1 60 16 21 22 18 19 15 14 13 48 49 50 51 SCM, Self-Check PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6*/IRQ2 PC7*/IRQ1 NDLY** VDD VDD VSS VSS OSC1 OSC2 XOSC1 XOSC2 VLCD1 VLCD2 VLCD3 BP3/PD3 BP2/PD2 BP1/PD1 BP0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I/O I/O I/O I/O I/O I/O I I I I I O O I O I O I I I O O O O Pin Number 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 SCM, Self-Check FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O * Open Drain Only when Output ** The NDLY pin should be connected to VDD. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 16 Freescale Semiconductor Functional Pin Description 1.5.1 VDD and VSS Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. 1.5.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the 2-pin on-chip oscillator. The OSC1 and OSC2 pins can accept: * A crystal as shown in Figure 1-3(a) * An external clock signal as shown in Figure 1-3(b) The frequency, fOSC, of the oscillator or external clock source is divided by 64 to produce the internal operating frequency, fOP, by default. 1.5.2.1 Crystal or Ceramic Resonator The circuit in Figure 1-3(a) shows a typical 2-pin oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup feedback resistor of ROF between OSC1 and OSC2 may be selected as a mask option for MC68HC05L16. Typical ROF resistor value is 5.5 M. MCU MASK OPTIONS ROF MCU OSC1 OSC2 4 MHz (TYP) OSC1 OSC2 UNCONNECTED CO1 CO2 EXTERNAL CLOCK (a) Crystal Connections (b) External Clock Source Connection Figure 1-3. Oscillator Connections MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 17 General Description 1.5.2.2 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3. This configuration is possible regardless of how the oscillator is set up. 1.5.3 XOSC1 and XOSC2 The XOSC1 and XOSC2 pins are the connections for the 2-pin on-chip oscillator. The XOSC1 and XOSC2 pins can accept: * A crystal as shown in Figure 1-4(a) * An external clock signal as shown in Figure 1-4(b) The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP, if selected by SYS1-SYS0 bits. When XOSC is not used, the XOSC1 pin must be connected to the RESET pin to ensure proper initialization of the clock circuitry. XOSC2 pin should remain unconnected. 1.5.3.1 Crystal Resonator The circuit in Figure 1-4(a) shows a typical 2-pin oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup feedback resistor of RXOF between XOSC1 and XOSC2 and a damping resistor of RXOD in series to XOSC2 may be selected as a mask option. Typical RXOF resistor value is 15 M, and RXOD resistor value is 1 M. MCU MASK OPTIONS RXOF MCU RXOD XOSC1 XOSC2 XOSC1 XOSC2 32.768 kHz (TYP) UNCONNECTED CXO1 CXO2 EXTERNAL CLOCK (a) Crystal Connections (b) External Clock Source Connection Figure 1-4. Oscillator Connections MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 18 Freescale Semiconductor Functional Pin Description 1.5.3.2 External Clock An external clock from another CMOS-compatible device can be connected to the XOSC1 input, with the XOSC2 input not connected, as shown in Figure 1-4(b). This configuration is possible regardless of how the oscillator is set up. 1.5.4 RESET This pin can be used as an input to reset the MCU to a known startup state by pulling it to the low state. When power is removed, the RESET pin contains a steering diode to discharge any voltage on the pin to VDD. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. An internal RESET pin pullup resistor may be selected as a mask option. A typical pullup resistor value is 46 k. 1.5.5 Port A (PA0-PA7) Port A is an 8-bit I/O port. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. Port A outputs may be configured as open-drain outputs and connected to a pullup resistor by software option. 1.5.6 Port B (PB0-PB7/KWI0-KWI7) Port B is an 8-bit input-only port that shares its lines with the key wakeup interrupt (KWI) system. Port B has a pullup option by software option. 1.5.7 Port C (PC0/SDI, PC1/SDO, PC2/SCK, PC3/TCAP, PC4/EVI, PC5/EVO, PC6/IRQ2, and PC7/IRQ1) Port C is an 8-bit I/O port. The state of any pin is software programmable and all port C lines are configured as inputs during power-on or reset. All port C lines may connect to a pullup resistor by software option. * Bits PC0-PC2 are shared with the SSPI subsystem and may be configured as open-drain outputs. * Bit 3 is shared with the TCAP pin of timer 1 and may be configured as an open-drain output. * Bit 4 is shared with the EVI bit of timer 2 and may be configured as an open-drain output. * Bit 5 is shared with the EVO bit of timer 2 and may be configured as an open-drain output. * Bit 6 is shared with the IRQ2 input. This bit is an open-drain output-only pin configured as an output. * Bit 7 is shared with the IRQ1 input. This bit is an open-drain output-only pin configured as an output. 1.5.8 Port D (PD1-PD3/BP1-BP3 and PD4-PD7/FP34-FP27) Port D is a 7-bit output-only port that shares its bits with the LCD backplane/frontplane drivers. Port D lines are configured as LCD outputs during power-on or reset. PD1-PD3 and PD4-PD7 outputs may be configured as open-drain outputs by a software option. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 19 General Description 1.5.9 Port E (PE0-PE7/FP38-FP35) Port E is an 8-bit output-only port that shares its bits with LCD frontplane drivers. Port E lines are configured as LCD outputs during power-on or reset. PE0-PE3 and PE4-PE7 outputs may be configured as open-drain outputs by a software option. 1.5.10 VLCD1, VLCD2, and VLCD3 These pins provide offset to the LCD driver bias for adjusting the contrast of the LCD. 1.5.11 NDLY This pin is reserved for factory test and should be connected to VDD in single-chip mode (user mode). 1.6 Modes of Operation The MC68HC05L16 has two operating modes: * Single-chip mode (SCM) * Self-check mode Single-chip mode, also called user mode, allows maximum use of pins for on-chip peripheral functions. The self-check capability of MC68HC05L16 provides an internal check to determine if the device is functional. 1.6.1 Mode Entry Mode entry is done at the rising edge of the RESET pin. Once the device enters one of the modes, the mode cannot be changed by software. Only an external reset can change the mode. At the rising edge of the RESET pin, the device latches the states of IRQ1 and IRQ2 and places itself in the specified mode. While the RESET pin is low, all pins are configured as single-chip mode. Table 1-2 shows the states of IRQ1 and IRQ2 for each mode entry. High voltage VTST = 2 x VDD is required to select modes other than single-chip mode. Table 1-2. Mode Select Summary Modes Single-Chip (User) Mode Self-Check Mode RESET PC6/IRQ1 VSS or VDD VTST PC7/IRQ2 VSS or VDD VDD MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 20 Freescale Semiconductor Modes of Operation SINGLE-CHIP MODE RESET VDD VSS VTST IRQ1 VDD VSS IRQ2 VTST = 2 x VDD VDD VSS Figure 1-5. Mode Entry Diagram 1.6.2 Single-Chip Mode (SCM) In this mode, all address and data bus activity occurs within the MCU. Thus, no external pins are required for these functions. The single-chip mode allows the maximum number of I/O pins for on-chip peripheral functions, for example, ports A through E, and LCD drivers. 1.6.3 Self-Check Mode In this mode, the reset vector is fetched from a 496-byte internal self-check ROM at $FE00-$FFEF. The self-check ROM contains a self-check program to test the functions of internal modules. Since this mode is not a normal user mode, all of the privileged control bits are accessible. This allows the self-check mode to be used for self- test of the device. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 21 General Description MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 22 Freescale Semiconductor Chapter 2 Memory Map 2.1 Introduction The MC68HC05L16 contains a 16,384-byte mask ROM, 496 bytes of self-check ROM, and 512 bytes of RAM. An additional 16 bytes of mask ROM are provided for user vectors at $FFF0-$FFFF. The MCU's memory map is shown in Figure 2-1. $0000 I/O 64 BYTES $003F $0040 63 64 0 $0000 DUAL-MAPPED I/O REGISTERS 16 BYTES $000F $0010 0015 0016 0000 RAM 512 BYTES $00C0 $00FF $023F $0240 UNUSED $0FFF $1000 MASK ROM 16 KBYTES $4FFF $5000 UNUSED $FDFF $FE00 SELF-CHECK ROM 496 BYTES $FFDF $FFE0 $FFEF $FFF0 $FFFF STACK 64 BYTES 191 192 255 256 575 576 I/O 48 BYTES 4095 4096 $003F 0063 20479 20480 65023 65024 TEST VECTORS USER VECTORS 65503 65504 65519 65520 65535 Figure 2-1. Memory Map MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 23 Memory Map 2.2 Input/Output and Control Registers The input/output (I/O) and control registers reside in locations $0000-$003F. A summary of these registers is shown in Figure 2-3. The bit assignments for each register are shown in Figure 2-4. Reading from unimplemented bits (denoted by shading) will return unknown states (unless explicitly defined to read 0), and writing to unimplemented bits will have no effect. See also Figure 2-2. Register Address (Main map unless otherwise specified) Register Name (Full) Read Read: Miscellaneous Register Write: (MISC) Bit Name (Mnemonic) Read-Only Bit FTUP * STUP * 0 0 0 0 SYS1 1 SYS0 0 FOSCE 1 OPTM 0 $003E Reset: Write Register Name (Mnemonic) Reset Value Read/Write Bit Figure 2-2. Register Description Key 2.2.1 Read/Write Bits Read/write bits are typically control bits. They are, in general, not modified by a module. Reset indicates the initial value of the latch. 2.2.2 Read-Only Bits Read-only bits are status flag bits. They are indicators of module status. Reset indicates the value that will be read immediately after system reset or before the module is enabled. 2.2.3 Write-Only Bits Write-only bits are control bits. They typically return a state of 0 to prevent an inadvertent write to this bit by a READ-MODIFY-WRITE instruction. Reset indicates the value that will be read immediately after system reset, which is the forced read value (typically 0). 2.2.4 Reserved Bits Reserved bits are read-only bits that typically read 0. Writes to these bits are ignored, and the user should not write 1 for future compatibility. Reset indicates the value that will be read immediately after system reset which is the forced read value (typically 0). 2.2.5 Reset Value Values specified on the row marked Reset: are initial values of register bits after system reset. Those bits unaffected by reset are marked with the letter U. Those bits that are unaffected by reset but initialized by power-on reset are marked with an asterisk (*). MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 24 Freescale Semiconductor Summary of Internal Registers and I/O Map 2.2.6 Option Map Address locations $0000-$000F are dual mapped. When the OPTM bit in the MISC register is cleared, the main address map is accessed. When the OPTM bit in the MISC register is set, the option address map is accessed. NOTE Although not necessary for this device, for future compatibility the OPTM bit should be cleared when accessing memory locations $0010 and above. 2.3 Summary of Internal Registers and I/O Map Figure 2-3 contains a detailed memory map of the I/O registers. Addr. $0000 Register Name Port A Data Register Read: (PORTA) Write: See page 52. Reset: Port B Data Register Read: (PORTB) Write: See page 53. Reset: Port C Data Register Read: (PORTC) Write: See page 54. Reset: Port D Data Register Read: (PORTD) Write: See page 56. Reset: Port E Data Register Read: (PORTE) Write: See page 57. Reset: Reserved Reserved Interrupt Control Register Read: (INTCR) Write: See page 45. Reset: Interrupt Status Register Read: (INTSR) Write: See page 46. Reset: Serial Peripheral Control Register Read: (SPCR) Write: See page 73. Reset: Bit 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0 Unaffected by reset PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 $0001 Unaffected by reset PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 $0002 Unaffected by reset PD7 1 PE7 1 R R IRQ1E 0 IRQ1F 0 SPIE 0 PD6 1 PE6 1 R R IRQ2E 0 IRQ2F 0 SPE 0 PD5 1 PE5 1 R R 0 0 0 0 DORD 0 PD4 1 PE4 1 R R KWIE 0 KWIF 0 MSTR 0 R PD3 1 PE3 1 R R IRQ1S 0 0 RIRQ1 0 0 0 = Reserved PD2 1 PE2 1 R R IRQ2S 0 0 RIRQ2 0 0 0 PD1 1 PE1 1 R R 0 0 0 0 0 0 U = Unaffected 1 1 PE0 1 R R 0 0 0 RKWIF 0 SPR 0 $0003 $0004 $0005 $0007 $0008 $0009 $000A = Unimplemented Figure 2-3. Main I/O Map (Sheet 1 of 5) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 25 Memory Map Addr. $000B Register Name Serial Peripheral Status Register Read: (SPSR) Write: See page 74. Reset: Serial Peripheral Data Register (SP- Read: DR) Write: See page 75. Reset: Reserved Reserved Timebase Control Register 1 Read: (TBCR1) Write: See page 88. Reset: Timebase Control Register 2 Read: (TBCR2) Write: See page 88. Reset: Timer Control Register Read: (TCR) Write: See page 80. Reset: Timer Status Register Read: (TSR) Write: See page 81. Reset: Input Capture Register High Read: (ICH) Write: See page 80. Reset: Input Capture Register Low Read: (ICL) Write: See page 80. Reset: Output Compare Register 1 High Read: (OC1H) Write: See page 79. Reset: Output Compare Register 1 Low Read: (OC1L) Write: See page 79. Reset: Timer Counter Register High Read: (TCNTH) Write: See page 88. Reset: Bit 7 SPIF 0 MSB 6 DCOL 0 BIT 6 5 0 0 BIT 5 4 0 0 BIT 4 3 0 0 BIT 3 2 0 0 BIT 2 1 0 0 BIT 2 Bit 0 0 0 LSB $000C $000D $000F Unaffected by reset R R R R R R R R R R R R R R R R $0010 TBCLK 0 TBIF 0 ICIE 0 ICF U BIT 15 0 0 TBIE 0 OC1IE 0 OC1F U BIT 14 LCLK 0 TBR1 1 TOIE 0 TOF U BIT 13 0 0 TBR0 1 0 0 0 0 BIT 12 0 0 0 RTBIF 0 0 0 0 0 BIT 11 0 0 0 0 0 0 0 0 BIT 10 T2R1 0 0 COPE 0 IEDG U 0 0 BIT 9 T2R0 0 0 COPC 0 OLVL 0 0 0 BIT 8 $0011 $0012 $0013 $0014 Unaffected by reset BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0015 Unaffected by reset BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 $0016 Unaffected by reset BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0017 Unaffected by reset BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 $0018 Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-3. Main I/O Map (Sheet 2 of 5) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 26 Freescale Semiconductor Summary of Internal Registers and I/O Map Addr. $0019 Register Name Timer Counter Register Low Read: (TCNTL) Write: See page 88. Reset: Alternate Timer Counter Register Read: High (ACNTH) Write: See page 79. Reset: Alternate Timer Counter Register Read: Low (ACMTL) Write: See page 79. Reset: Timer Control Register 2 Read: (TCR2) Write: See page 85. Reset: Timer Status Register 2 Read: (TSR2) Write: See page 87. Reset: Output Compare Register 2 Read: (OC2) Write: See page 87. Reset: Timer Counter Register 2 Read: (TCNT2) Write: See page 88. Reset: LCD Control Register Read: (LCDCR) Write: See page 100. Reset: LCD Data Register 1 Read: (LCDR1) Write: See page 101. Reset: LCD Data Register 2 Read: (LCDR2) Write: See page 101. Reset: LCD Data Register 3 Read: (LCDR3) Write: See page 101. Reset: LCD Data Register 4 Read: (LCDR4) Write: See page 101. Reset: Bit 7 BIT 7 6 BIT 6 5 BIT 5 4 BIT 4 3 BIT 3 2 BIT 2 1 BIT 1 Bit 0 BIT 0 Unaffected by reset BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 $001A Unaffected by reset BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $001B Unaffected by reset TI2IE 0 TI2F 0 BIT 7 0 BIT 7 0 LCDE 0 F1B3 OC2IE 0 OC2F 0 BIT 6 0 BIT 6 0 DUTY1 0 F1B2 0 0 0 0 BIT 5 0 BIT 5 0 DUTY0 0 F1B1 T2CLK 0 0 0 BIT 4 0 BIT 4 0 0 0 F1B0 IM2 0 0 RTI2F 0 BIT 3 0 BIT 3 0 PEH 0 F0B3 IL2 0 0 ROC2F 0 BIT 2 0 BIT 2 0 PEL 0 F0B2 OE2 0 0 0 BIT 1 0 BIT 1 0 PDH 0 F0B1 OL2 0 0 0 BIT 0 0 BIT 0 1 0 0 F0B0 $001C $001D $001E $001F $0020 $0021 Unaffected by reset F3B3 F3B2 F3B1 F3B0 F2B3 F2B2 F2B1 F2B0 $0022 Unaffected by reset F5B3 F5B2 F5B1 F5B0 F4B3 F4B2 F4B1 F4B0 $0023 Unaffected by reset F7B3 F7B2 F7B1 F7B0 F6B3 F6B2 F6B1 F6B0 $0024 Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-3. Main I/O Map (Sheet 3 of 5) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 27 Memory Map Addr. $0025 Register Name LCD Data Register 5 Read: (LCDR5) Write: See page 101. Reset: LCD Data Register 6 Read: (LCDR6) Write: See page 101. Reset: LCD Data Register 7 Read: (LCDR7) Write: See page 101. Reset: LCD Data Register 8 Read: (LCDR8) Write: See page 101. Reset: LCD Data Register 9 Read: (LCDR9) Write: See page 101. Reset: LCD Data Register 10 Read: (LCDR10) Write: See page 101. Reset: LCD Data Register 11 Read: (LCDR11) Write: See page 101. Reset: LCD Data Register 12 Read: (LCDR12) Write: See page 101. Reset: LCD Data Register 13 Read: (LCDR13) Write: See page 101. Reset: LCD Data Register 14 Read: (LCDR14) Write: See page 101. Reset: LCD Data Register 15 Read: (LCDR15) Write: See page 101. Reset: LCD Data Register 16 Read: (LCDR16) Write: See page 101. Reset: Bit 7 F9B3 6 F9B2 5 F9B1 4 F9B0 3 F8B3 2 F8B2 1 F8B1 Bit 0 F8B0 Unaffected by reset F11B3 F11B2 F11B1 F11B0 F10B3 F10B2 F10B1 F10B0 $0026 Unaffected by reset F13B3 F13B2 F13B1 F13B0 F12B3 F12B2 F12B1 F12B0 $0027 Unaffected by reset F15B3 F15B2 F15B1 F15B0 F14B3 F14B2 F14B1 F14B0 $0028 Unaffected by reset F17B3 F17B2 F17B1 F17B0 F16B3 F16B2 F16B1 F16B0 $0029 Unaffected by reset F19B3 F19B2 F19B1 F19B0 F18B3 F18B2 F18B1 F18B0 $002A Unaffected by reset F21B3 F21B2 F21B1 F21B0 F20B3 F20B2 F20B1 F20B0 $002B Unaffected by reset F23B3 F23B2 F23B1 F23B0 F22B3 F22B2 F22B1 F22B0 $002C Unaffected by reset F25B3 F25B2 F25B1 F25B0 F24B3 F24B2 F24B1 F24B0 $002D Unaffected by reset F27B3 F27B2 F27B1 F27B0 F26B3 F26B2 F26B1 F26B0 $002E Unaffected by reset F29B3 F29B2 F29B1 F29B0 F28B3 F28B2 F28B1 F28B0 $002F Unaffected by reset F31B3 F31B2 F31B1 F31B0 F30B3 F30B2 F30B1 F30B0 $0030 Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-3. Main I/O Map (Sheet 4 of 5) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 28 Freescale Semiconductor Option Map for I/O Configurations Addr. $0031 Register Name LCD Data Register 17 Read: (LCDR17) Write: See page 101. Reset: LCD Data Register 18 Read: (LCDR18) Write: See page 101. Reset: LCD Data Register 19 Read: (LCDR19) Write: See page 101. Reset: LCD Data Register 20 Read: (LCDR20) Write: See page 101. Reset: Reserved Reserved Miscellaneous Register Read: (MISC) Write: See page 67. Reset: Reserved Bit 7 F33B3 6 F33B2 5 F33B1 4 F33B0 3 F32B3 2 F32B2 1 F32B1 Bit 0 F32B0 Unaffected by reset F35B3 F35B2 F35B1 F35B0 F34B3 F34B2 F34B1 F34B0 $0032 Unaffected by reset F37B3 F37B2 F37B1 F37B0 F36B3 F36B2 F36B1 F36B0 $0033 Unaffected by reset $0034 $0035 $003D 0 0 0 0 F38B3 F38B2 F38B1 F38B0 Unaffected by reset R R FTUP * R R R STUP * R R R 0 0 R R R 0 0 R R R R R R R R R R $003E $003F SYS1 1 R = Reserved SYS0 0 R FOSCE 1 R OPTM 0 R * Unaffected by reset but initialized by power-on reset = Unimplemented U = Unaffected Figure 2-3. Main I/O Map (Sheet 5 of 5) 2.4 Option Map for I/O Configurations Most of the I/O configurations are done in the option map (Figure 2-4). Some options still remain as mask options for the MC68HC05L16 such as a pullup resistor for the RESET pin and resistors for the OSC1/OSC2 and XOSC1/XOSC2 pins. These mask options may be read by the MOSR ($000F) in the option map. The option map is located at $0000-$000F of the main memory map and it is available when the OPTM bit in the MISC register ($003E) is set. Main registers at $0000-$000F are not available when OPTM = 1. I/O port data direction registers are contained in the option map in Figure 2-4. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 29 Memory Map Addr. $0000 $0001 Register Name Port A Data Direction Register Read: (DDRA) Write: See page 52. Reset: Reserved Port C Data Direction Register Read: (DDRC) Write: See page 55. Reset: Port D MUX Register Read: (PDMUX) Write: See page 56. Reset: Port E MUX Register Read: (PEMUX) Write: See page 57. Reset: Reserved Reserved Resistor Control Register 1 Read: (RCR1) Write: See page 31. Reset: Resistor Control Register 2 Read: (RCR2) Write: See page 31. Reset: Bit 7 DDRA7 0 R 6 DDRA6 0 R 5 DDRA5 0 R 4 DDRA4 0 R 3 DDRA3 0 R 2 DDRA2 0 R 1 DDRA1 0 R Bit 0 DDRA0 0 R $0002 DDRC7 0 PDM7 0 PEM7 0 R R DDRC6 0 PDM6 0 PEM6 0 R R DDRC5 0 PDM5 0 PEM5 0 R R DDRC4 0 PDM4 0 PEM4 0 R R DDRC3 0 0 0 PEM3 0 R R DDRC2 0 0 0 PEM2 0 R R DDRC1 0 0 0 PEM1 0 R R DDRC0 0 0 0 PEM0 0 R R $0003 $0004 $0005 $0007 $0008 0 0 RC7 0 0 0 RC6 0 DWOML 0 1 1 R R 0 0 RC5 0 EWOMH 0 CWOM5 0 R R 0 0 RC4 0 EWOML 0 CWOM4 0 R R RBH 0 RC3 0 0 0 CWOM3 0 R R RBL 0 RC2 0 0 0 CWOM2 0 R R RAH 0 RC1 0 AWOMH 0 CWOM1 0 R R RAL 0 RC0 0 AWOML 0 CWOM0 0 R R $0009 $000A Open-Drain Output Control Read: DWOMH Register 1 (WOM1) Write: See page 32. Reset: 0 Open-Drain Output Control Read: Register 2 (WOM2) Write: See page 32. Reset: Reserved Reserved Key Wakeup Input Enable Register Read: (KWIEN) Write: See page 33. Reset: Mask Option Status Register Read: (MOSR) Write: See page 33. Reset: 1 1 R R $000B $000C $000D $000E KWIE7 0 RSTR U KWIE6 0 OSCR U KWIE5 0 XOSCR U KWIE4 0 0 0 R KWIE3 0 0 0 = Reserved KWIE2 0 0 0 KWIE1 0 0 0 KWIE0 0 0 0 $000F = Unimplemented U = Unaffected Figure 2-4. Option Map MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 30 Freescale Semiconductor Option Map for I/O Configurations 2.4.1 Resistor Control Register 1 Address: Read: Write: Reset: Option Map -- $0008 Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 RBH 0 2 RBL 0 1 RAH 0 Bit 0 RAL 0 Figure 2-5. Resistor Control Register 1 (RCR1) Bits 7-4 -- Reserved These bits are not used and always read as logic 0. RBH -- Port B Pullup Resistor (H) When this bit is set, pullup resistors are connected to the upper four bits of port B. This bit is cleared on reset. RBL -- Port B Pullup Resistor (L) When this bit is set, pullup resistors are connected to the lower four bits of port B. This bit is cleared on reset. RAH -- Port A Pullup Resistor (H) When this bit is set, pullup resistors are connected to the upper four bits of port A. This bit is cleared on reset. RAL -- Port A Pullup Resistor (L) When this bit is set, pullup resistors are connected to the lower four bits of port A. This bit is cleared on reset. 2.4.2 Resistor Control Register 2 Address: Read: Write: Reset: Option Map -- $0009 Bit 7 RC7 0 6 RC6 0 5 RC5 0 4 RC4 0 3 RC3 0 2 RC1 0 1 RC1 0 Bit 0 RC0 0 Figure 2-6. Resistor Control Register 2 (RCR2) RCx -- Port C Pullup Resistor (Bitx) When RCx bit is set, the pullup resistor is connected to the corresponding bit of port C. This bit is cleared on reset. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 31 Memory Map 2.4.3 Open-Drain Output Control Register 1 Address: Read: Write: Reset: Option Map -- $000A Bit 7 DWOMH 0 6 DWOML 0 5 EWOMH 0 4 EWOML 0 3 0 0 2 0 0 1 AWOMH 0 Bit 0 AWOML 0 Figure 2-7. Open-Drain Output Control Register 1 (WOM1) DWOMH -- Port D Open-Drain Mode (H) When this bit is set, the upper four bits of port D are configured as open-drain outputs if these bits are selected as port D output by the PDH bit in the LCDCR. This bit is cleared on reset. DWOML -- Port D Open-Drain Mode (L) When this bit is set, the lower three bits of port D are configured as open-drain outputs if the corresponding BPx pin is not used by the LCD driver. This bit is cleared on reset. EWOMH -- Port E Open-Drain Mode (H) When this bit is set, the upper four bits of port E (that are configured as I/O output by the PEH bit in the LCDCR) are configured as open-drain outputs. This bit is cleared on reset. EWOML -- Port E Open-Drain Mode (L) When this bit is set, the lower four bits of port E (that are configured as I/O output by the PEL bit in the LCDCR) are configured as open-drain outputs. This bit is cleared on reset. Bits 3 and 2 -- Reserved These bits are not used and always return to logic 0. AWOMH -- Port A Open-Drain Mode (H) When this bit is set, the upper four bits of port A that are configured as output (corresponding to the DDRA bit set) become open-drain outputs. This bit is cleared on reset. AWOML -- Port E Open-Drain Mode (L) When this bit is set, the lower four bits of port A that are configured as output (corresponding DDRA bit set) become open-drain outputs. This bit is cleared on reset. 2.4.4 Open-Drain Output Control Register 2 Address: Read: Write: Reset: Option Map -- $000B Bit 7 1 1 6 1 1 5 CWOM5 0 4 CWOM4 0 3 CWOM3 0 2 CWOM2 0 1 CWOM1 0 Bit 0 CWOM0 0 Figure 2-8. Open-Drain Output Control Register 2 (WOM2) Bits 7 and 6 -- Reserved These bits are not used and always read as logic 1. When configured as output, PC6 and PC7 are always open drain. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 32 Freescale Semiconductor Option Map for I/O Configurations CWOMx -- Port C Open-Drain Mode (Bitx) When CWOMx bit is set, port C bits x are configured as open-drain outputs if DDRCx is set. This bit is cleared on reset. 2.4.5 Key Wakeup Input Enable Register Address: Read: Write: Reset: Option Map -- $000E Bit 7 KWIE7 0 6 KWIE6 0 5 KWIE5 0 4 KWIE4 0 3 KWIE3 0 2 KWIE2 0 1 KWIE1 0 Bit 0 KWIE0 0 Figure 2-9. Key Wakeup Input Enable Register (KWIEN) KWIEx -- Key Wakeup Input Enable (Bitx) When KWIEx bit is set, the KWIx (PBx) input is enabled for key wakeup interrupt. This bit is cleared on reset. 2.4.6 Mask Option Status Register The mask option status register (MOSR) indicates the state of mask options specified prior to production of the MC68HC05L16. Address: Read: Write: Reset: U U = Unimplemented U 0 U = Unaffected 0 0 0 0 Option Map -- $000F Bit 7 RSTR 6 OSCR 5 XOSCR 4 0 3 0 2 0 1 0 Bit 0 0 Figure 2-10. Mask Option Status Register (MOSR) RSTR -- RESET Pin Pullup Resistor When this bit is set, it indicates an internal pullup resistor is attached to the RESET pin by mask option. OSCR -- OSC Feedback Resistor When this bit is set, it indicates that an internal feedback resistor is attached between OSC1 and OSC2 by mask option. XOSCR -- OSC Feedback Resistor When this bit is set, it indicates that an internal feedback resistor is attached between XOSC1 and XOSC2. The damping resistor at the XOSC2 pin is attached by mask option. Bits 4-0 -- Reserved These bits are not used and always read as logic 0. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 33 Memory Map 2.5 RAM The 512-byte internal RAM is positioned at $0040-$023F in the memory map. The lower 192 bytes are positioned in the page zero which are accessible by the direct addressing mode. The upper 64 bytes of this area (page zero) are used for the CPU stack. Care should be taken if the stack area is used for data storage. The remaining 320 bytes of RAM, $0100-$023F, are accessed by extended addressing mode. The RAM is implemented with static cells and retains its contents during the stop and wait modes. 2.6 Self-Check ROM Self-check ROM is 496 bytes of mask ROM positioned at $FE00-$FFEF. This ROM contains self-check programs and reset/interrupt vectors in the self-check mode. 2.7 Mask ROM The 16,384-byte user ROM is positioned at $1000-$4FFF, and an additional 16 bytes of ROM are located at $FFF0-$FFFF for user vectors. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 34 Freescale Semiconductor Chapter 3 Central Processor Unit (CPU) 3.1 Introduction This section describes the central processor unit (CPU). 3.2 CPU Registers The MCU contains five registers as shown in Figure 3-1. The interrupt stacking order is shown in Figure 3-2. 7 A 7 X 15 PC 15 0 0 0 0 0 0 0 0 7 1 0 1 SP CCR NZ STACK POINTER CONDITION CODE REGISTER 0 PROGRAM COUNTER 0 INDEX REGISTER 0 ACCUMULATOR H I C Figure 3-1. Programming Model 7 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL UNSTACK NOTE: 0 STACK I N T E R R U P T DECREASING MEMORY ADDRESSES Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. Figure 3-2. Stacking Order MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 35 Central Processor Unit (CPU) 3.3 Accumulator The accumulator (A) is a general-purpose, 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 7 A 0 3.4 Index Register The index register (X) is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area. 7 X 0 3.5 Condition Code Register The condition code register (CCR) is a 5-bit register in which the H, N, Z, and C bits are used to indicate the results of the instruction just executed, and the I bit is used to enable or disable interrupts. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. CCR H I N Z C Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the I bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is affected also during bit test and branch instructions and during shifts and rotates. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 36 Freescale Semiconductor Stack Pointer 3.6 Stack Pointer The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the 10 most significant bits are permanently set to 0000000011. These eight 0 bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and looses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 15 0 0 0 0 0 0 0 0 7 1 1 SP 0 3.7 Program Counter The program counter (PC) is a 16-bit register that contains the address of the next byte to be fetched. 15 PC 0 3.8 Arithmetic/Logic Unit The arithmetic/logic unit (ALU) performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal processor cycles to complete this chain of operations. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 37 Central Processor Unit (CPU) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 38 Freescale Semiconductor Chapter 4 Resets and Interrupts 4.1 Introduction In user operating modes, the reset/interrupt vectors are located at the top of the address space ($FFF0-$FFFF). In self-check mode, the reset/interrupt vectors are located at $FFE0-$FFEF in the internal self-check ROM. Descriptions in this section assume a user operating mode is in use. Table 4-1 shows the address assignments for the vectors. Table 4-1. Interrupt Vector Assignments Vector Address FFF0-FFF1 FFF2-FFF3 FFF4-FFF5 SSPI Timer 2 TI2I OC2I ICI OC1I TOI IRQ1 IRQ2 Interrupt Source Timebase Masked by I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit None COP RESET Pin Power-On None None None Local Mask TBIE SPIE TI2IE OC2IE ICIE OC1IE TOIE KWIE IRQ1E IRQ2E None COPE None None Priority (1 = Highest) 7 6 5 5 4 4 4 3 2 2 Same Level as an Instruction 1 1 1 FFF6-FFF7 FFF8-FFF9 FFFA-FFFB FFFC-FFFD Timer 1 KWI IRQ SWI FFFE-FFFF Reset Upon reset, the I bit in the condition code register is set and interrupts are disabled (masked). When an interrupt occurs, the I bit is set automatically by hardware after stacking the condition code register (CCR). All interrupts in the MC68HC05L16 follow a fixed hardware priority circuit to resolve simultaneous requests. Each interrupt has a software programmable interrupt mask bit which may be used to selectively inhibit automatic hardware response. In addition, the I bit in the CCR acts as a class inhibit mask to inhibit all sources in the I-bit class. RESET and software interrupt (SWI) are not masked by the I bit in the CCR. SWI is an instruction rather than a prioritized asynchronous interrupt source. In a sense, it is lower in priority than any source because once any interrupt sequence has begun, SWI cannot override it. In another sense, it is higher in priority than any hardware sources, except reset, because once the SWI opcode is fetched, no other sources can be honored until after the first instruction in the SWI service routine has been executed. SWI causes the I mask bit in the CCR to be set. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 39 Resets and Interrupts 4.2 Interrupts There are six hardware interrupt sources in the MC68HC05L16: * IRQ1 and IRQ2 * Key wakeup interrupt (KWI) * Timer 1 (TOI, ICI, and OC1I) * Timer 2 (TI2I and OC2I) * Serial transfer complete interrupt (SSPI) * Timebase interrupt (TBI) 4.2.1 IRQ1 and IRQ2 Two external interrupt request inputs, IRQ1 and IRQ2, share the same vector address at $FFFA and $FFFB. Bits IRQ1S and IRQ2S in interrupt control register (INTCR) control whether IRQ1 and IRQ2, respectively, respond only to the falling edge or falling edge and low level to trigger an interrupt. The IRQ1 and IRQ2 are enabled by IRQ1E and IRQ2E bits and IRQ1F and IRQ2F bits are provided as an indicator in the interrupt status register (INTSR). Since the IRQ1(2)F can be set by either the pins or the data latches of PC7(6), be sure to clear the flags by software before setting the IRQ1(2)E bit. The IRQ1 and the IRQ2 pins are shared with port C bit 7 and bit 6, respectively, and IRQx pin states can be determined by reading port C pins. The BIL and BIH instructions apply only to the IRQ1 input. 4.2.2 Key Wakeup Interrupt (KWI) Eight key wakeup inputs (KWI0-KWI7) share pins with port B. Each key wakeup input is enabled by the corresponding bit in the KWIEN register which resides in the option map, and KWI is enabled by the KWIE bit in the INTCR. When a falling edge is detected at one of the enabled key wakeup inputs, the KWIF bit in the INTSR is set and KWI is generated if KWIE = 1. Each input has a latch which responds only to the falling edge at the pin, and all input latches are cleared at the same time by clearing the KWIF bit. See Figure 4-6. 4.2.3 IRQ (KWI) Software Consideration IRQ and KWI interrupts have a timing delay in a case described in Figure 4-2. This section shows programming for proper interrupts with IRQ or KWI. Figure 4-1 shows an example of timer1 interrupt. In this case, the interrupt by TOF occurs as soon as the TOIE (timer1 overflow interrupt enable) bit is set. . . CLI BSET TOIE, TCR LDA #$55 . . . TOF Interrupt pending Interrupt occurs before this instruction Figure 4-1. Timer 1 Interrupt MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 40 Freescale Semiconductor Interrupts Figure 4-2 shows an example of IRQ1 interrupt. In this case, the interrupt occurs after execution the instruction following the instruction which sets IRQ1E bit. The similar action occurs against IRQ2 and KWI interrupts. . . CLI BSET IRQ1E, INTCR LDA #$55 . . . IRQ1 interrupt pending Interrupt occurs after this instruction Figure 4-2. IRQ Timing Delay This problem can be solved by using a software patch like Figure 4-3. A similar procedure could be used for IRQ2 or KWI. . . CLI BSET IRQ1E, INTCR NOP LDA #$55 . . IRQ1 interrupt pending Interrupt occurs after this instruction Figure 4-3. Software Patch for IRQ1 4.2.4 Timer 1 Interrupt Three timer 1 interrupts (TOI, ICI, and OC1I) share the same interrupt vector at $FFF6 and $FFF7. See 9.2 Timer 1. 4.2.5 Timer 2 Interrupt Two timer 2 interrupts (TI2I and OC2I) share the same interrupt vector at $FFF4 and $FFF5. See 9.3.1 Timer Control Register 2. 4.2.6 SSPI Interrupt The SSPI transfer complete interrupt uses the vector at $FFF2 and $FFF3. See Chapter 8 Simple Serial Peripheral Interface (SSPI). 4.2.7 Timebase Interrupt The timebase interrupt uses the vector at $FFF0 and $FFF1. See 7.5 Timebase. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 41 Resets and Interrupts FROM RESET Y I BIT IN CCR SET ? N IRQ EXTERNAL INTERRUPT N INTERNAL INTERRUPT(1) N Y Y CLEAR IRQ REQUEST LATCH STACK PC, X, A, CCR FETCH NEXT INSTRUCTION SET I BIT IN CC REGISTER SWI INSTRUCTION ? N RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR, A, X, PC EXECUTE INSTRUCTION Y Y LOAD PC FROM SWI: $FFFC-$FFFD IRQx: $FFFA-$FFFB KWI: $FFF8-$FFF9 TIMER 1: $FFF6-$FFF7 TIMER 2: $FFF4-$FFF5 SSPI: $FFF2-$FFF3 TBI: $FFF0-$FFF1 1. KWI, timer 1, timer 2, SSPI, and TBI Figure 4-4. Interrupt Flowchart MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 42 Freescale Semiconductor Interrupts FOR BIH/BIL 0 SEL H IRQ1 (PC7) D C R IRQ1S IRQ1F R Q 1 S Q DATA BUS READ INSTRUCTION RESET/POR RITE 1 TO RIRQ1 IRQ1E INT IRQ2E WRITE 1 TO RESET/POR IRQ2S IRQ2 (PC6) H R C D Q SEL 1 R IRQ2F Q S DATA BUS READ INSTRUCTION 0 Figure 4-5. IRQ1 and IRQ2 Block Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 43 Resets and Interrupts KWIE0 H KWI0 (PB0) D C Q R KWIE1 H KWI1 (PB1) D C Q R KWI2 TO KWI6 S READ KWIF KWIE7 Q KWIF R DATA BUS H KWI7 (PB7) D C R Q RESET/POR WRITE 1 TO RKWIF KWIE KWI Figure 4-6. Key Wakeup Interrupt (KWI) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 44 Freescale Semiconductor Interrupt Control Register 4.3 Interrupt Control Register Address: Read: Write: Reset: $0008 Bit 7 IRQ1E 0 6 IRQ2E 0 5 0 0 4 KWIE 0 3 IRQ1S 0 2 IRQ2S 0 1 0 0 Bit 0 0 0 Figure 4-7. Interrupt Control Register (INTCR) IRQ1E -- IRQ1 Interrupt Enable The IRQ1E bit enables IRQ1 interrupt when IRQ1F is set. This bit is cleared on reset. 0 = IRQ1 interrupt disabled 1 = IRQ1 interrupt enabled IRQ2E -- IRQ2 Interrupt Enable The IRQ2E bit enables IRQ2 interrupt when IRQ2F is set. This bit is cleared on reset. 0 = IRQ2 interrupt disabled 1 = IRQ2 interrupt enabled Bit 5 -- Reserved This bit is not used and is always read as logic 0. KWIE -- Key Wakeup Interrupt (KWI) Enable The KWIE bit enables key wakeup interrupt when KWIF is set. This bit is cleared on reset. 0 = KWI disabled 1 = KWI enabled IRQ1S -- IRQ1 Select Edge Sensitive Only 0 = IRQ1 configured for low level and negative edge sensitive 1 = IRQ1 configured to respond only to negative edges IRQ2S -- IRQ2 Select Edge Sensitive Only 0 = IRQ2 configured for low level and negative edge sensitive 1 = IRQ2 configured to respond only to negative edges Bits 1 and 0 -- Reserved These bits are not used and always read as logic 0. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 45 Resets and Interrupts 4.4 Interrupt Status Register Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 $0009 Bit 7 IRQ1F 6 IRQ2F 5 0 4 KWIF 3 0 RIRQ1 0 2 0 RIRQ2 0 1 0 0 Bit 0 0 RKWIF 0 Figure 4-8. Interrupt Status Register (INTSR) IRQ1F -- IRQ1 Interrupt Flag When IRQ1S = 0, the falling edge or low level at the IRQ1 pin sets IRQ1F. When IRQ1S = 1, only the falling edge sets the IRQ1F bit. If the IRQ1E bit and this bit are set, an interrupt is generated. This read-only bit is cleared by writing a logic 1 to the RIRQ1 bit. Reset clears this bit. IRQ2F -- IRQ2 Interrupt Flag When IRQ2S = 0, the falling edge or low level at the IRQ2 pin sets IRQ2F. When IRQ2S = 1, only the falling edge sets the IRQ2F bit. If the IRQ2E bit and this bit are set, an interrupt is generated. This read-only bit is cleared by writing a logic 1 to the RIRQ2 bit. Reset clears this bit. Bit 5 -- Reserved This bit is not used and is always read as logic 0. KWIF -- Key Wakeup Interrupt Flag When the KWIEx bit in the KWIEN register is set, the falling edge at the KWIx pin sets the KWIF bit. If the KWIE bit and this bit are set, an interrupt is generated. This read-only bit is cleared by writing a logic 1 to the RKWIF bit. Reset clears this bit. RIRQ1 -- Reset IRQ1 Flag The RIRQ1 bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the IRQ1F bit and writing logic 0 to this bit has no effect. RIRQ2 -- Reset IRQ2 Flag The RIRQ2 bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the IRQ2F bit and writing a logic 0 to this bit has no effect. Bit 1 -- Reserved This bit is not used and is always read as logic 0. RKWIF -- Reset KWI Flag The RKWIF bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the KWIF bit and writing a logic 0 to this bit has no effect. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 46 Freescale Semiconductor Chapter 5 Low-Power Modes 5.1 Introduction The MCU has two power-saving modes, stop and wait. Flowcharts of these modes are shown in Figure 5-2. 5.2 Stop Mode The STOP instruction places the MCU in its lowest-power mode. In stop mode, the internal main oscillator OSC is turned off, halting all internal processing, including timer operations (timer 1, timer 2, and computer operating properly (COP) watchdog timer). Suboscillator XOSC does not stop oscillating. Therefore, if XOSC is used as the clock source for the COP watchdog timer, COP is still functional in stop mode. See Chapter 7 Oscillators/Clock Distributions. During stop mode, the timer prescaler is cleared. The I bit in the condition code register (CCR) is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of stop mode only by RESET or an interrupt from IRQ1, IRQ2, KWI, SSPI (slave mode only), or TBI. See Chapter 7 Oscillators/Clock Distributions. 5.3 Wait Mode The WAIT instruction places the MCU in a low-power mode, but wait mode consumes more power than stop mode. All CPU action is suspended, but on-chip peripherals and oscillators remain active. Any interrupt or reset (including a COP reset) will cause the MCU to exit wait mode. During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The timers may be enabled to allow a periodic exit from wait mode. Wait mode must be exited and the COP must be reset to prevent a COP timeout. The reduction of power in wait mode depends on how many of the on-chip peripheral's clocks can be shut down. Therefore, the amount of power that will be consumed is dependent on the application, and it would be prohibitive to test all parts for all variations. For these reasons, the values given in Chapter 12 Electrical Specifications reflect typical application conditions after initial characterization of silicon. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 47 Low-Power Modes STATE A CPU: PH2: X1: X2: RUN X1/2 ON ON RESET INT STATE B CPU: PH2: X1: X2: RUN X1/4 ON ON STATE C CPU: PH2: X1: X2: RUN X1/64 ON ON STATE A STATE B STATE C STOP STATE D CPU: PH2: X1: X2: RUN X2/2 ON ON DELAY RESET INT STOP X1EN = 0 X1EN = 1 RESET INT STOP STATE E CPU: PH2: X1: X2: RUN X2/2 OFF ON POWER-ON STATE D STATE E INT Notes: PH2 is at same frequency as internal processor clock E. X1 = OSC X2 = XOSC X1EN = FOSCE Low Power High Speed STOP E D C B A Figure 5-1. Clock State and STOP Recovery/Power-On Reset Delay Diagrams MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 48 Freescale Semiconductor Wait Mode STOP WAIT STOP OSCILLATOR OSC AND ALL CLOCKS EXCEPT XOSC CLEAR I BIT OSCILLATOR ACTIVE TIMER CLOCK ACTIVE PROCESSOR CLOCKS STOPPED CLEAR I BIT N RESET? N Y Y Y EXTERNAL INTERRUPT IRQ? N KWI INTERRUPT ? N TIMER 1 INTERRUPT ? N TIMER 2 INTERRUPT ? N SSPI INTERRUPT ? N TIMEBASE INTERRUPT ? N 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE RESET? EXTERNAL INTERRUPT IRQ? N KWI INTERRUPT ? N Y Y Y Y SSPI INTERRUPT ? N Y TIMEBASE N INTERRUPT ? Y IF FOSC = 1 TURN ON OSCILLATOR OSC WAIT FOR TIME RESTART PROCESSOR CLOCK Y Y Y Notes: Slave Mode Only When TBCLK = 0 Figure 5-2. Stop/Wait Flowcharts MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 49 Low-Power Modes MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 50 Freescale Semiconductor Chapter 6 Parallel Input/Output (I/O) 6.1 Introduction The MCU has five parallel ports: * Port A has eight I/O pins. * Port B has eight input/only pins. * Port C has eight I/O pins. * Port D has seven output-only pins. * Port E has eight output-only pins. Most of these 39 I/O pins serve multiple purposes depending on the configuration of the MCU system. The configuration is in turn controlled by hardware mode selection as well as internal control registers. DATA DIRECTION REGISTER BIT INTERNAL HC05 CONNECTIONS LATCHED OUTPUT DATA BIT OUTPUT I/O PIN INPUT REG BIT INPUT I/O Figure 6-1. Port I/O Circuitry for One Bit MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 51 Parallel Input/Output (I/O) 6.2 Port A Port A is an 8-bit, bidirectional, general-purpose port. The data direction of a port A pin is determined by its corresponding DDRA bit. When a port A pin is programmed as an output by the corresponding DDRA bit, data in the PORTA data register becomes output data to the pin. This data is returned when the PORTA register is read. Open drain or CMOS outputs are selected by AWOMH and AWOML bits in the WOM1 register. If the AWOMH bit is set, the P-channel drivers of bits 7-4 output buffers are disabled (open drain). If the AWOML bit is set, the P-channel drivers of bits 3-0 output buffers are disabled (open drain). When a bit is programmed as input by the corresponding DDRA bit, the pin level is read by the CPU. Port A has optional pullup resistors. When the RAH bit or RAL bit in the RCR1 is set, pullup resistors are attached to the upper four bits or lower four bits of port A pins, respectively. When a pin outputs a low level, the pullup resistor is disconnected regardless of the RAH or RAL bit state. 6.2.1 Port A Data Register Address: Read: Write: Reset: $0000 Bit 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0 Unaffected by reset Figure 6-2. Port A Data Register (PORTA) Read Anytime; returns pin level if DDR set to input; returns output data latch if DDR set to output Write Anytime; data stored in an internal latch; drives pin only if DDR set for output Reset Becomes high-impedance input 6.2.2 Port A Data Direction Register Address: Read: Write: Reset: Option Map -- $0000 Bit 7 DDRA7 0 6 DDRA6 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0 Figure 6-3. Port A Data Direction Register (DDRA) Read Anytime when OPTM = 1 Write Anytime when OPTM = 1 Reset Cleared to $00; all general-purpose I/O configured for input MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 52 Freescale Semiconductor Port B DDRAx -- Port A Data Direction Register Bit x 0 = Configure I/O pin PAx to input 1 = Configure I/O pin PAx to output 6.3 Port B Port B pins serve two basic functions: KWI input pins and general-purpose input pins. Each KWI input is enabled or disabled by the corresponding KWIEx bit in the KWIEN register, and the usage of the KWI input does not affect the general-purpose input function. Port B pin states may be read any time regardless of the configurations. Since there is no output drive logic associated with port B, there is no DDRB register and the write to the PORTB register has no meaning. Port B has optional pullup resistors. When the RBH or RBL bit in the RCR1 is set, pullup resistors are attached to the upper four bits or lower four bits of port A pins, respectively. Address: Read: Write: Reset: $0001 Bit 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 Bit 0 PB0 Unaffected by reset Figure 6-4. Port B Data Register (PORTB) Read Anytime; returns pin level Write Has no meaning or effect Reset Unaffected; always an input port 6.4 Port C Port C pins share functions with several on-chip peripherals. A pin function is controlled by the enable bit of each associated peripheral. Bit 7 and bit 6 of port C are general-purpose I/O pins and IRQ input pins. The DDRC7 and DDRC6 bits determine whether the pin states or the data latch states should be read by the CPU. Since IRQ1F or IRQ2F can be set by either the pins or the data latches, when using IRQs, be sure to clear the flags by software before enabling the IRQ1E or IRQ2E bits. When configured for output port, PC6 and PC7 are open drain only. When VDD output is required, a pullup resistor must be enabled. The PC5 pin is a general-purpose I/O pin and the direction of the pin is determined by the DDRC5 bit in the data direction register C (DDRC). When the event output (EVO) is enabled, the PC5 is configured as an event output pin and the DDRC5 bit has meaning only for the read of PC5 bit in the PORTC register; if the DDRC5 is set, the PC5 data latch is read by the CPU. Otherwise, PC5 pin level (EVO state) is read. When EVO is disabled, the DDRC5 bit decides the idling state of EVO (if DDRC5 = 1). MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 53 Parallel Input/Output (I/O) The PC4 and PC3 pins share functions with the timer input pins (EVI and TCAP). These bits are not affected by the usage of timer input functions and the directions of pins are always controlled by the DDRC4 and DDRC3 bits. Also, the DDRC4 and DDRC3 bits determine whether the pin states or data latch states should be read by the CPU. NOTE Since the TCAP pin is shared with the PC3 I/O pin, changing the state of the PC3 DDR or data register can cause an unwanted TCAP interrupt. This can be handled by clearing the ICIE bit before changing the configuration of PC3 and clearing any pending interrupts before enabling ICIE. Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should always be cleared whenever EVI is used. EVI should not be used when DDRC4 is high. The PC2-PC0 pins are shared with the simple serial peripheral interface (SSPI). When the SSPI is not used (SPE = 0), DDRC2-DDRC0 bits control the direction of the pins, and when the SSPI is enabled, the pins are configured as serial clock output or input (SCK), serial data output (SDO), and serial data input (SDI). The direction of the SCK depends on the MSTR bit in the SPCR. When PORTC is read, the value read will be determined by the data direction register. When the port is configured for input (DDRC2, DDRC1, or DDRC0 equal to logic 0) the pin state is read. When the port is configured for output (DDRC2, DDRC1, or DDRC0 equal to logic 0), the output data latch is read. Port C has optional pullup resistors. When the RCx bit in the RCR2 is set, pullup resistors are attached to the PCx pin. When a pin outputs a low level, the pullup resistor is disconnected regardless of an RCR2 register bit being set Bits 5-0 have open drain or CMOS output options, which are controlled by the corresponding WOM2 register bits. These open drain or CMOS output options may be selected for either the general-purpose output ports or the peripheral outputs (EVO, SCK, and SDO). 6.4.1 Port C Data Register Address: Read: Write: Reset: $0002 Bit 7 PC7 6 PC6 5 PC5 4 PC4 3 PC3 2 PC2 1 PC1 Bit 0 PC0 Unaffected by reset Figure 6-5. Port C Data Register (PORTC) Read Anytime; returns pin level if DDR set to input; returns output data latch if DDR set to output Write Anytime; data stored in an internal latch; drives pin only if DDR set for output writes do not change pin state when pin configured for SDO, SCK, and EVO peripheral output Reset Becomes high-impedance input MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 54 Freescale Semiconductor Port D 6.4.2 Port C Data Direction Register Address: Read: Write: Reset: Option Map -- $0002 Bit 7 DDRC7 0 6 DDRC6 0 5 DDRC5 0 4 DDRC4 0 3 DDRC3 0 2 DDRC2 0 1 DDRC1 0 Bit 0 DDRC0 0 Figure 6-6. Port C Data Direction Register (DDRC) Read Anytime when OPTM = 1 Write Anytime when OPTM = 1 Reset Cleared to $00; all general-purpose I/O configured for input DDRCx -- Port C Data Direction Register Bit x The timer and SSPI force the I/O state to be an output for each port C line associated with an enabled output function such as SDO and EVO. For these cases, the data direction bits will not change. 0 = Configure I/O pin PCx to input 1 = Configure I/O pin PCx to output 6.5 Port D Port D pins serve one of two basic functions depending on the MCU mode selected: * LCD frontplane and backplane driver outputs * General-purpose output pins Since port D is an output-only port, there is no DDRD register. Instead of DDRD, port D MUX control register (PDMUX) is used. Bits 7-4 of this register control the port/LCD muxing of port D bits 7-4, respectively, on a bit-wide basis. These bits are cleared on reset, and writing a logic 1 to any bit will turn that pin into a port output. This function is superseded by the PDH bit in the LCD control register. When PDH is set, the upper four bits of port D become port outputs regardless of the state of the PDMUX bits. On reset, all port D outputs are disconnected from the pins and the port D data latches are set to a logic 1. The pin connections of the lower three bits of port D depend on the LCD duty selection by the DUTY1 and DUTY0 bits in the LCDCR. When the LCD duty is not 1/4, the unused backplane driver(s) is (are) replaced by the port D output pin(s) automatically. If DWOMH bit or DWOML bit in the WOM1 register is set, the P-channel drivers of output buffers at the upper four bits or lower three bits, respectively, are disabled (open-drain mode). These open-drain controls do not apply to the pins which are configured as frontplane or backplane driver outputs. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 55 Parallel Input/Output (I/O) 6.5.1 Port D Data Register Address: Read: Write: Reset: $0003 Bit 7 PD7 1 6 PD6 1 5 PD5 1 4 PD4 1 3 PD3 1 2 PD2 1 1 PD1 1 Bit 0 1 1 Figure 6-7. Port D Data Register (PORTD) Read Anytime; returns output data latch; bit 0 is always read logic 1 Write Anytime (Writes do not change pin state when configured for LCD driver output.) Reset All bits set to logic 1 and output ports disconnected from the pins (LCD is enabled on reset.) 6.5.2 Port D MUX Register Address: Read: Write: Reset: Option Map -- $0003 Bit 7 PDM7 0 6 PDM6 0 5 PDM5 0 4 PDM4 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 6-8. Port D MUX Register (PDMUX) Read Anytime (When OPTM = 1, bits 3-0 always read logic 0.) Write Anytime (Writes have no effect if PDH is set.) Reset All bits cleared; LCD enabled PDMx -- Port D MUX Control bit x 0 = Configure pin PDx to LCD 1 = Configure pin PDx to output 6.6 Port E Port E pins serve one of two basic functions depending on the MCU mode selected: * LCD frontplane driver outputs * General-purpose output pins Since port E is an output-only port, there is no DDRE register. Instead of DDRE, port E MUX control register (PEMUX) is used. Bits 7-0 of this register control the port/LCD muxing of port E bits 7-0 respectively on a bit-wide basis. These bits are cleared on reset, and writing a logic 1 to any bit will turn that pin into a port output. This function is superseded by the PEH and PEL bits in the LCD control register. When PEH is set, the upper four bits of port E become port outputs regardless of the state of the PEMUX bits. Likewise, when PEL is set, the lower four bits of port E become outputs. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 56 Freescale Semiconductor Port E On reset, all port E outputs are disconnected from the pins and the port E data latches are set to logic 1. If EWOMH bit or EWOML bit in the WOM1 register is set, the P-channel driver of output buffers at the upper or lower four bits, respectively, are disabled (open-drain mode). These open-drain controls do not apply to the pins which are configured as frontplane driver outputs. 6.6.1 Port E Data Register Address: Read: Write: Reset: $0004 Bit 7 PE7 1 6 PE6 1 5 PE5 1 4 PE4 1 3 PE3 1 2 PE2 1 1 PE1 1 Bit 0 PE0 1 Figure 6-9. Port E Data Register (PORTE) Read Anytime; returns output data latch Write Anytime (Writes do not change pin state when configured for LCD driver output.) Reset All bits set to logic 1 and output ports disconnected from the pins (LCD is enabled on reset.) 6.6.2 Port E MUX Register Address: Read: Write: Reset: Option Map -- $0004 Bit 7 PEM7 0 6 PEM6 0 5 PEM5 0 4 PEM4 0 3 PEM3 0 2 PEM2 0 1 PEM1 0 Bit 0 PEM0 0 Figure 6-10. Port E MUX Register (PEMUX) Read Anytime when OPTM = 1 Write Anytime (Writes have no effect if PEH/PEL is set.) Reset All bits cleared (LCD is enabled.) PEMx -- Port E MUX Control Bit x 0 = Configure pin PEx to LCD 1 = Configure pin PEx to output MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 57 Parallel Input/Output (I/O) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 58 Freescale Semiconductor Chapter 7 Oscillators/Clock Distributions 7.1 Introduction There are two oscillator blocks: OSC and XOSC. Several combinations of the clock distributions are allowed for the modules in the MC68HC05L16. Refer to Figure 7-1. FOSCE/ PWRON OSC1 OSC OSC2 OSC DIVIDER 7-BIT 1/20 1/21 1/25 WAIT SEL 1/2 CPU SYSTEM CLOCK SYS1 SYS0 SSPI TIMER 1 CLK CTRL POR 6-BIT FTUP TIMER 2 EXCLK 1/27 XOSC1 XOSC XOSC2 XCLK TIMEBASE 1/27 STOP Figure 7-1. Clock Signal Distribution 7.2 OSC Clock Divider and POR Counter The OSC clock is divided by a 7-bit counter which is used for the system clock, timebase, and power-on reset (POR) counter. Clocks divided by 2, 4, and 64 are available for the system clock selections and a clock divided by 128 is provided for the timebase and POR counter. The POR counter is a 6-bit clock counter that is driven by the OSC divided by 128. The overflow of this counter is used for setting FTUP bit, releasing the POR, and resuming operation from stop mode. The 7-bit divider and POR counter are initialized to $0078 by two conditions: * Power-on detection * When FOSCE bit is cleared MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 59 LCD DRIVER AND PORTS Oscillators/Clock Distributions 7.3 System Clock Control The system clock is provided for all internal modules except timebase. Both OSC and XOSC are available as the system clock source. The divide ratio is selected by the SYS1 and SYS0 bits in the MISC register. (See Table 7-1.) By default, OSC/64 is selected on reset. Table 7-1. System Bus Clock Frequency Selection SYS1 SYS0 0 0 1 1 0 1 0 1 Divide Ratio OSC / 2 OSC / 4 OSC / 64 XOSC / 2 CPU Bus Frequency (Hz) OSC = 4.0 M 2.0 M 1.0 M 62.5 k -- OSC = 4.1943 M 2.0972 M 1.0486 M 65.536 k -- XOSC = 32.768 k -- -- -- 16.384 k NOTE Do not switch the system clock to XOSC (SYS1 and SYS0 = 11) when XOSC clock is not available. The XOSC clock is available when STUP flag is set. Do not switch the system clock to OSC (SYS1 and SYS0 = 00, 01, or 10) when OSC clock is not available. The OSC clock is available when FTUP flag is set. 7.4 OSC and XOSC The secondary oscillator (XOSC) runs continuously after power up. The main oscillator (OSC) can be stopped to conserve power via the STOP instruction or the FOSCE bit in the MISC register. The effects of restarting the OSC will vary depending on the current state of the MCU, including SYS0, SYS1, and FOSCE. 7.4.1 OSC on Line If the system clock is OSC, FOSCE should remain logic 1. Executing the STOP instruction in this condition will halt OSC, put the MCU into a low-power mode, and clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ or reset re-starts the oscillator. When the POR counter overflows, internal reset is released and execution can begin. The stabilization time will vary between 8064 and 8192 counts. NOTE Exiting STOP with external reset will always return the MCU to the state as defined by the default register definitions, for example, SYS0:SYS1 = 1:0, FOSCE = 1. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 60 Freescale Semiconductor OSC and XOSC OSC OSC1 Rf MASK OPTION ON CHIP OFF CHIP OSC2 XOSC1 XOSC XOSC2 Rf MASK OPTION Rd Figure 7-2. OSC1, OSC2, XOSC1, and XOSC2 Mask Options 7.4.2 XOSC on Line If XOSC is the system clock (SYS:SYS1 = 1:1), OSC can be stopped either by the STOP instruction or by clearing the FOSCE bit. The suboscillator (XOSC) never stops except during power down. This clock also may be used as the clock source of the system clock and timebase. STUP bit indicates that the XOSC clock is available. OSC and XOSC pins have options for feedback and damping resistor implementations. These options are set through mask option and may be read through the MOSR register. NOTE When XOSC is not used, the XOSC1 input pin should be connected to the RESET pin. RESET LOGIC RESET ON CHIP OFF CHIP XOSC1 XOSC XOSC2 NO CONNECT FROM EXTERNAL RESET CIRCUIT Figure 7-3. Unused XOSC1 Pin 7.4.2.1 XOSC with FOSCE = 1 If the system clock is XOSC and FOSCE = 1, executing the STOP instruction will halt OSC, put the MCU into a low-power mode and clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ re-starts the oscillator; however, execution begins immediately using XOSC. When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the system clock. The stabilization time will vary between 8064 and 8192 counts. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 61 Oscillators/Clock Distributions 7.4.2.2 XOSC with FOSCE = 0 If XOSC is the system clock, clearing FOSCE will stop OSC and preset the 7-bit divider and 6-bit POR counter to $0078. Execution will continue with XOSC and when FOSCE is set again, OSC will re-start. When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the system clock. The stabilization time will be 8072 counts. 7.4.2.3 XOSC with FOSCE = 0 and STOP If XOSC is the system clock and FOSCE is cleared, further power reduction can be achieved by executing the STOP instruction. In this case, OSC is stopped, the 7-bit divider and 6-bit POR counter are preset to $0078 (since FOSCE = 0) and execution is halted. Exiting STOP with external IRQ does not re-start the OSC; however, execution begins immediately using XOSC. OSC may be re-started by setting FOSCE. When the POR counter overflows, FTUP will be set, signaling that OSC is stable and can be used as the system clock. The stabilization time will be 8072 counts. 7.4.2.4 Stop Mode and Wait Mode During stop mode, the main oscillator (OSC) is shut down and the clock path from the second oscillator (XOSC) is disconnected. All modules except timebase are halted. Entering stop mode clears the FTUP flag in the MISC register and initializes the POR counter. Stop mode is exited by RESET, IRQ1, IRQ2, KWI, SSPI (slave mode), or timebase interrupt. If OSC is selected as the system clock source during stop mode, CPU resumes after the overflow of the POR counter and this overflow also sets the FTUP status flag. If XOSC is selected as the system clock source during stop mode, no stop recovery time is required for exiting stop mode because XOSC never stops. Re-start of the main oscillator depends on the FOSCE bit. During wait mode, only the CPU clocks are halted and the peripheral modules are not affected. Wait mode is exited by RESET and any interrupts. Table 7-2. Recovery Time Requirements Before Reset or Interrupt CPU Clock Source -- OSC (OSC on) OSC (OSC off) XOSC (OSC on) XOSC (OSC off) Stop -- Out Out In In(1) Out Out In In FOSCE -- 1 0(2) 1 0(1) 1 0 1 0 Power-On Reset Wait -- -- -- -- -- -- -- -- External Reset -- No wait Wait Wait Wait No wait Wait Wait Wait Exit Stop Mode by Interrupt -- -- -- Wait Wait -- -- No wait No wait 1. This case never occurs. 2. This case has no meaning for the applications. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 62 Freescale Semiconductor Timebase 7.5 Timebase Timebase is a 14-bit up-counter which is clocked by XOSC input or OSC input divided by 128. TBCLK bit in the TBCR1 register selects the clock source. This 14-bit divider is initialized to $0078 only upon power-on reset (POR). After counting 8072 clocks, the STUP bit in the MISC register is set. The divided clocks from the timebase are used for LCDCLK, STUP, TBI, and COP. (See Figure 7-4). 7.5.1 LCDCLK The clocks divided by 64 and 128 are used as LCD clocks at the LCD driver module, and clocks are selected by the LCLK bit in the TBCR1. TBCLK LCLK 1 OSC/27 XCLK 0 SEL 7-BIT DIVIDER 1/26 1/27 0 SEL 1 1/20 1/25 1/26 1/27 TBR1 TBIE LCD CLOCK 7-BIT DIVIDER SEL TBIF TBI TBR0 COP RESET COP CLEAR DIVIDE BY 4 COP ENABLE Figure 7-4. Timebase Clock Divider 7.5.2 STUP Timebase divider is initialized to $0078 by the power-on detection. When the count reaches 8072, the STUP flag in the MISC register is set. Once the STUP flag is set, it is never cleared until power down. 7.5.3 TBI Timebase interrupts may be generated every 0.5, 0.25, 0.125, or 0.0039 seconds with a 32.768-kHz crystal at XOSC pins. The timebase interrupt flag (TBIF) is set every period and interrupt is requested if the enable bit (TBIE) is set. The clock divided by 128, 4096, 8192, or 16,384 is used to set TBIF, and this clock is selected by the TBR1 and TBR0 bits in the TBCR2 register. (See Table 7-3.) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 63 Oscillators/Clock Distributions Table 7-3. Timebase Interrupt Frequency TBCR2 TBR 1 0 0 1 1 TBR 0 0 1 0 1 Divide Ratio TBCLK / 128 TBCLK / 4096 TBCLK / 8192 TBCLK / 16,384 OSC = 4.0 M 244 7.63 3.81 1.91 Frequency (Hz) OSC = 4.1943 M 256 8.00 4.00 2.00 XOSC = 32.768 k 256 8.00 4.00 2.00 7.5.4 COP The computer operating properly (COP) watchdog timer is controlled by the COPE and COPC bits in the TBCR2 register. The COP uses the same clock as TBI that is selected by the TBR1 and TBR0 bits. The TBI is divided by four and overflow of this divider generates COP timeout reset if the COP enable (COPE) bit is set. The COP timeout reset has the same vector address as POR and external RESET. To prevent the COP timeout, the COP divider is cleared by writing a logic1 to the COP clear (COPC) bit. When the timebase divider is driven by the OSC clock, clock for the divider is suspended during stop mode or when FOSCE is a logic 0. This may cause COP period stretching or no COP timeout reset when processing errors occur. To avoid these problems, it is recommended that the XOSC clock be used for the COP functions. When the timebase (COP) divider is driven by the XOSC clock, the divider does not stop counting and the COPC bit must be triggered to prevent the COP timeout. Table 7-4. COP Timeout Period TBCR2 TBR1 0 0 1 1 TBR0 0 1 0 1 OSC = 4.0 MHz Min 12.3 393 786 1573 Max 16.4 524 1048 2097 COP Period (ms) OSC = 4.1943 MHz Min 11.7 375 750 1500 Max 15.6 500 1000 2000 XOSC = 32.768 kHz Min 11.7 375 750 1500 Max 15.6 500 1000 2000 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 64 Freescale Semiconductor Timebase 7.5.5 Timebase Control Register 1 Address: Read: Write: Reset: $0010 Bit 7 TBCLK 0 6 0 0 5 LCLK 0 4 0 0 3 0 0 2 0 0 1 T2R1 0 Bit 0 T2R0 0 Figure 7-5. Timebase Control Register 1 (TBCR1) Read Anytime Write Anytime (Only one write is allowed on bit 7 after reset.) TBCLK -- Timebase Clock The TBCLK bit selects the timebase clock source. This bit is cleared on reset. After reset, write to this bit is allowed only once. 0 = XOSC clock selected 1 = OSC clock divided by 128 selected Bit 6 -- Reserved This bit is not used and always reads as logic 0. LCLK -- LCD Clock The LCLK bit selects the clock for the LCD driver. This bit is cleared on reset. 0 = Divide by 64 selected 1 = Divide by 128 selected Bits 4-2 -- Reserved These bits are not used and always read as logic 0. T2R1 and T2R0 -- Timer 2 Prescale Rate Select Bits T2R1 and T2R0 select timer 2 clock rate. See 9.3 Timer 2 for more detail. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 65 Oscillators/Clock Distributions 7.5.6 Timebase Control Register 2 Address: Read: Write: Reset: 0 $0011 Bit 7 TBIF 6 TBIE 0 = Unimplemented 5 TBR1 1 4 TBR0 1 3 0 RTBIF 0 2 0 0 1 0 COPE 0 Bit 0 0 COPC 0 Figure 7-6. Timebase Control Register 2 (TBCR2) Read Anytime (Bits 3 and 0 are write-only bits and always read as logic 0.) Write Anytime (Bit 7 is a read-only bit and write has no effect; bit 1 is 1-time write bit.) TBIF -- Timebase Interrupt Flag The TBIF bit is set every timeout interval of the timebase counter. This read-only bit is cleared by writing a logic 1 to the RTBIF bit. Reset clears the TBIF bit. The timebase interrupt period between reset and the first TBIF depends on the time elapsed during reset, since the timebase divider is not initialized on reset. TBIE -- Timebase Interrupt Enable The TBIE bit enables the timebase interrupt capability. If TBIF = 1 and TBIE = 1, the timebase interrupt is generated. 0 = Timebase interrupt disabled 1 = Timebase interrupt requested when TBIF = 1 TBR1 and TBR0 -- Timebase Interrupt Rate Select The TBR1 and TBR0 bits select one of four rates for the timebase interrupt period (see Table 7-3). The TBS rate is also related to the COP timeout reset period. These bits are set to logic 1 on reset. Table 7-5. Timebase Interrupt Frequency TBCR2 TBR1 0 0 1 1 TBR0 0 1 0 1 Divide Ratio TBCLK / 128 TBCLK / 4096 TBCLK / 8192 TBCLK / 16,384 Frequency (Hz) OSC = 4.0 M 244 7.63 3.81 1.91 OSC = 4.1943 M 256 8.00 4.00 2.00 XOSC = 32.768 k 256 8.00 4.00 2.00 RTBIF -- Reset TBS Interrupt Flag The RTBIF bit is a write-only bit and is always read as logic 0. Writing logic 1 to this bit clears the TBIF bit and writing logic 0 to this bit has no effect. Bit 2 -- Reserved This bit is not used and is always read as logic 0. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 66 Freescale Semiconductor Timebase COPE -- COP Enable When the COPE bit is logic 1, the COP reset function is enabled. This bit is cleared on reset (including COP timeout reset) and write to this bit is allowed only once after reset. COPC -- COP Clear Writing logic 1 to the COPC bit clears the 2-bit divider to prevent COP timeout. (The COP timeout period depends on the TBI rate.) This bit is a write-only bit and returns to logic 0 when read. 7.5.7 Miscellaneous Register Address: Read: Write: Reset: * * = Unimplemented 0 0 $003E Bit 7 FTUP 6 STUP 5 0 4 0 3 SYS1 1 2 SYS0 0 1 FOSCE 1 Bit 0 OPTM 0 * Unaffected by reset but initialized by power-on reset Figure 7-7. Miscellaneous Register (MISC) FTUP -- OSC Time Up Flag Power-on detection and clearing the FOSCE bit clears this read-only bit. This bit is set by the overflow of the POR counter. Reset does not affect this bit. 0 = During POR or OSC shut down 1 = OSC clock available for the system clock STUP -- XOSC Time Up Flag Power-on detection clears this read-only bit. This bit is set after the timebase has counted 8072 clocks. Reset does not affect this bit. 0 = XOSC not stabilized or no signal on XOSC1 and XOSC2 pins 1 = XOSC clock available for the system clock Bits 5 and 4 -- Reserved These bits are not used and always read as logic 0. SYS1 and SYS0 -- System Clock Select These two bits select the system clock source. On reset, the SYS1 and SYS0 bits are initialized to 1 and 0, respectively. NOTE Do not switch the system clock to XOSC (SYS1 and SYS0 = 11) when the XOSC clock is not available. The XOSC clock is available when the STUP flag is set. Do not switch the system clock to OSC (SYS1 and SYS 0 = 00, 01, or 10) when the OSC clock is not available. The OSC clock is available when the FTUP flag is set. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 67 Oscillators/Clock Distributions Table 7-6. System Bus Clock Frequency Selection SYS1 0 0 1 1 SYS0 0 1 0 1 Divide Ratio OSC / 2 OSC / 4 OSC / 64 XOSC / 2 CPU Bus Frequency (Hz) OSC = 4.0 M 2.0 M 1.0 M 62.5 k -- OSC = 4.1943 M 2.0972 M 1.0486 M 65.536 k -- XOSC = 32.768 k -- -- -- 16.384 k FOSCE -- Fast (Main) Oscillator Enable The FOSCE bit controls the main oscillator activity. This bit should not be cleared by the CPU when the main oscillator is selected as the system clock source. When this bit is cleared: 1. OSC is shut down. 2. 7-bit divider at the OSC input and POR counter are initialized to $0078. 3. FTUP flag is cleared. When this bit is set: 1. Main oscillator starts again. 2. FTUP flag is set by the POR counter overflow (8072 clocks). OPTM -- Option Map Select The OPTM bit selects one of two register maps at $0000-$000F. This bit is cleared on reset. 0 = Main register map selected 1 = Option map selected MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 68 Freescale Semiconductor Chapter 8 Simple Serial Peripheral Interface (SSPI) 8.1 Introduction The simple serial peripheral interface (SSPI) of the MC68HC05L16 is a master/slave synchronous serial communication module. SSPI uses a 3-wire protocol: data input, data output, and serial clock. In this format, the clock is not being included in the data stream and must be provided as a separate signal. When the SSPI is enabled (SPE = 1), bits 0-2 of port C become SDI (serial data in), SDO (serial data out), and SCK (serial clocK) pins. The corresponding DDRC bit does not change the direction of the pin. The MSTR bit decides the SSPI operation mode. The SCK pin is configured as output in master mode and configured as input in slave mode. The DORD bit in the serial peripheral control register (SPCR) selects the data transmission order. When DORD is set, the least significant bit (LSB) of serial data is shifted out/in first. When the DORD is clear, serial data is shifted from/to the most significant bit (MSB). Master serial clock speed is selected by the SPR bit in the SPCR. An interrupt may be generated by the completion of a transfer. 8.2 Features Features of the SSPI are: * Full-duplex, 3-wire synchronous transfers * Master or slave operation * Programmable data transmission order, LSB or MSB first * 1.05-MHz (maximum) transmission bit frequency at 2.1-MHz CPU bus frequency at 5 Vdc * Two programmable transmission bit rates * End-of-transmission interrupt flag * Wakeup from stop mode (slave mode only) 8.3 Functional Descriptions In master mode, the clock start logic is triggered by the CPU (detection of a CPU write to the 8-bit shift register (SPDR)). The SCK is based on the internal processor clock. This clock is also used in the 3-bit counter and 8-bit shift register. See Figure 8-2. When data is written to the 8-bit shift register of the master device, it is then shifted out to the SDO pin for application to the slave device. At the same time, data applied from the slave device via the SDI pin is shifted into the 8-bit shift register. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 69 Simple Serial Peripheral Interface (SSPI) After 8-bit data is shifted in/out, SCK stops and SPIF is set. If SPIE is enabled, an interrupt request is generated. The slave device in stop mode wakes up by this interrupt. Further transfers (writes to SPDR) are inhibited while SPIF is a logic 1. The master-slave basic interconnection is illustrated in Figure 8-1. MASTER DEVICE SDO SPDR HFF SDI SLAVE DEVICE SPDR HFF SCK SCK CLOCK GENERATOR CLOCK GENERATOR SDI SDO Figure 8-1. SSPI Master-Slave Interconnection 8.4 Internal Block Descriptions This following paragraphs describe the main blocks in the SSPI module. (See Figure 8-2). HC05 INTERNAL BUS INTERRUPT CONTROLS AND ADDRESS BUS CONTROL LOGIC DATA BUS 0 000 00 SPSR S P I F D C O L S T A R T S P E 000 SPCR MS SP TR R SPDR HFF SDO DORD SDI CLOCK GENERATOR SCK Figure 8-2. SSPI Block Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 70 Freescale Semiconductor Signal Descriptions 8.4.1 Control This block is an interface to the HC05 internal bus and generates a start signal when a write to the SPDR is detected in master mode. It also generates an interrupt request to the CPU. 8.4.2 SPDR This serial peripheral data register (SPDR) is an 8-bit shift register. The DORD bit in the SPCR determines the bus connection between the internal data bus and SPDR. This register can be read and written by the CPU. 8.4.3 SPCR Bits in the serial peripheral control register (SPCR) control SSPI functions. 8.4.4 SPSR The serial peripheral status register (SPSR) mainly sets flags such as SPIF and DCOL. 8.4.5 CLKGEN In master mode, this block generates SCK when the CPU writes to the data register (SPDR) and the clock rate is selected by the SPR bit in the control register. In slave mode, the external clock from the SCK pin is used instead of the master mode clock, and SPR has no affect. This clock generator includes a 3-bit clock counter. Overflow of this counter sets SPIF. 8.5 Signal Descriptions Three basic signals -- SDI, SDO, and SCK -- are described in the following subsections. The relationship among SCK, SDI, and SDO is shown in Figure 8-3. 8.5.1 SSPI Data I/O (SDI and SDO) The two serial data lines -- SDI for input and SDO for output -- are connected to PC0 and PC1, respectively, when SSPI is enabled (SPE = 1). At the falling edge of SCK, a serial data bit is transmitted out of the SDO pin. At the rising edge of SCK, a serial data bit on the SDI pin is sampled internally. When data is transmitted to other devices via the SDO line, the receiving data is shifted into the shift register through the SDI pin. This implies full- duplex transmission with both data-out and data-in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full status bits. A single status bit, SPIF, is used to signify the completion of data transfer. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 71 Simple Serial Peripheral Interface (SSPI) SCK SDO DORD = 0 MSB BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 LSB SDI DORD = 0 MSB BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 LSB SDO DORD = 1 LSB BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 MSB SDI DORD = 1 LSB BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 MSB DATA SAMPLE Figure 8-3. SSPI Clock-Data Timing Diagram 8.5.2 Serial Clock (SCK) SCK is used for synchronization of both input and output data streams through its SDI and SDO pins. The master and slave devices are capable of exchanging a data byte during a sequence of eight clock pulses. Since the SCK is generated by the master, slave data transfer is accomplished by synchronization to SCK. The master generates the SCK through a circuit driven by the internal processor clock and uses the SCK to latch incoming slave device data on the SDI pin and shift out data to the slave via the SDO pin. The SPR bit in the SPCR of the master selects the transmission clock rate. The slave device receives the SCK from the master device, and uses the SCK to latch incoming master device data on the SDI pin and shifts out data to the master via the SDO pin. The SPR bit in the SPCR of the slave has no meaning. NOTE PC2/SCK should be at VDD level before SSPI is enabled. This can be done with an internal or external pullup resistor or by setting DDRC2 = 1 and PC2 = 1 prior to enabling the SSPI. Otherwise, the circuit will not initialize correctly. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 72 Freescale Semiconductor Registers 8.6 Registers Three registers in the SSPI provide control, status, and data storage functions. They are: * Serial peripheral control register, SPCR location $000A * Serial peripheral status register, SPSR location $000B * Serial peripheral data register, SPDR location $000C 8.6.1 Serial Peripheral Control Register Address: Read: Write: Reset: $000A Bit 7 SPIE 0 6 SPE 0 5 DORD 0 4 MSTR 0 3 0 0 2 0 0 1 0 0 Bit 0 SPR 0 Figure 8-4. Serial Peripheral Control Register (SPCR) SPIE -- SSPI Interrupt Enable If the serial peripheral interrupt enable (SPIE) bit is set, an interrupt is generated when SPIF in the SPSR is set and I bit (interrupt mask bit) in the condition code register (CCR) is clear. During stop mode, an SSPI request is accepted only in slave mode. Interrupt in master mode will be pending until stop mode is exited. STOP instruction does not change SPIF and SPIE. 0 = Disable SSPI interrupt 1 = Enable SSPI interrupt SPE -- SSPI Enable When the SSPI enable (SPE) bit is set, the SSPI system is enabled and connected to the port C pins. Clearing the SPE bit initializes all control logic in the SSPI modules and disconnects the SSPI from port C pins. This bit is cleared on reset. 0 = Disable SSPI 1 = Enable SSPI DORD -- Data Transmission ORDer When this bit is set, the data in the 8-bit shift register (SPDR) is shifted in/out from the LSB. When this bit is cleared, the data in the SPDR is shifted in/out from the MSB. This bit is cleared on reset. 0 = MSB first 1 = LSB first MSTR -- MaSTeR Mode Select The MSTR bit determines whether the device is in master mode or slave mode. In master mode (MSTR = 1), the SCK pin is configured as an output and the serial clock is generated by the internal clock generator when the CPU writes to the SPDR. In slave mode (MSTR = 0), the SCK pin is configured as an input and the serial clock is applied externally. This bit is cleared on reset. 0 = Slave mode 1 = Master mode MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 73 Simple Serial Peripheral Interface (SSPI) Bits 3-1 -- Reserved These bits are not used and are fixed to 0. SPR -- SSPI Clock Rate Select This serial peripheral clock rate bit selects one of two bit rates of SCK. This bit is cleared on reset. 0 = Internal processor clock divided by 2 1 = Internal processor clock divided by 16 8.6.2 Serial Peripheral Status Register Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 $000B Bit 7 SPIF 6 DCOL 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Figure 8-5. Serial Peripheral Status Register (SPSR) SPIF -- Serial Transfer Complete Flag The serial peripheral data transfer complete flag bit notifies the user that a data transfer between the MC68HC05L16 and an external device has been completed. With the completion of the data transfer, the rising edge of the eighth pulse sets SPIF, and if SPIE is set, SSPI is generated. However, during STOP, the interrupt request is serviced only in slave mode. STOP execution never affects the SPIF flag or SPIE. When SPIF is set, the ninth clock from the clock generator or from the SCK pin is inhibited. Clearing the SPIF bit is done by a software sequence of accessing the SPSR while the SPIF bit is set followed by accessing SPDR (8-bit shift register). This also clears the DCOL bit. While SPIF is set, all writes to the SPDR are inhibited until SPSR is read by the CPU. The SPIF bit is a read-only bit and is cleared on reset. 0 = Data transfer not complete 1 = Data transfer complete DCOL -- Data COLlision The data collision bit notifies the user that an attempt was made to write or read the serial peripheral data register while a data transfer was taking place with an external device. The transfer continues uninterrupted; therefore, a write will be unsuccessful, and a data read will be incorrect. A data collision only sets the DCOL bit and does not generate an SSPI interrupt. The DCOL bit indicates only the occurrence of data collision. Clearing the DCOL bit is done by a software sequence of accessing the SPSR while SPIF is set followed by accessing the SPDR. Both the SPIF and DCOL bits will be cleared by this sequence. The DCOL bit is cleared on reset. 0 = No data collision 1 = Data collision occurred Bits 5-0 -- Reserved These bits are not used and are fixed to 0. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 74 Freescale Semiconductor Port Function 8.6.3 Serial Peripheral Data Register Address: Read: Write: Reset: $000C Bit 7 MSB 6 BIT 6 5 BIT 5 4 BIT 4 3 BIT 3 2 BIT 2 1 BIT 2 Bit 0 LSB Unaffected by Reset Figure 8-6. Serial Peripheral Data Register (SPDR) Read A read during transmission causes DCOL to be set. Write A write during transmission causes DCOL to be set. The SPDR is used to transmit and receive data on the serial bus. In master mode, a write to this register initiates transmission/reception of a data byte. The SPIF status bit is set at the completion of data byte transmission. A write to the SPDR is inhibited while this register is shifting (a write attempt sets DCOL) or when the SPIF bit is set without reading SPSR. Data collision never affects the receiving and transmitting data in SPDR. A write or read of the SPDR after accessing the SPSR with SPIF set will clear the SPIF and DCOL bits. The ability to access the SPDR is inhibited when a transmission is taking place. It is important to read the discussion defining the DCOL and SPIF bits to understand the limits on using the SPDR. When SSPI is not used (SPE = 0), the SPDR can be used as a general-purpose data storage register. 8.7 Port Function The SSPI shares I/O pins with PC0-PC2. When SPE is set, PC0 becomes SDI input, PC1 becomes SDO output and PC2 becomes SCK. The direction of SCK depends on the MSTR bit. Setting DDRC bits 0-2 does not change the data direction of the pin to output, but instead changes the source of data when PC0-PC2 is read. If DDRCx = 1, port C bit x data latch is read and if DDRCx = 0, PORTCx pin level is read by the CPU. When SPE is clear, SSPI is disconnected from the I/O pins and PC0-PC2 are used as general-purpose I/O pins. See 6.4 Port C. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 75 Simple Serial Peripheral Interface (SSPI) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 76 Freescale Semiconductor Chapter 9 Timer System 9.1 Introduction The MC68HC05L16 has two timer modules: timer 1 with a 16-bit counter and timer 2 with an 8-bit counter. Timer 1 has one input pin (TCAP) and no output pin. Timer 2 has one input pin (EVI) and one output pin (EVO). Figure 9-1 illustrates the timer system of MC68HC05L16. CAP OVF1 TIMER1 16-BIT COUNTER TCAP INPUT CONTROL 1 CLK1 CMP1 IEDG T2CLK EXCLK EVI INPUT CONTROL 2 CLK2 SEL TIMER2 8-BIT COUNTER CMP2 OUTPUT CONTROL EVO IM2 IL2 O L 2 O E 2 PH2 PRESCALER TIMER REGISTERS Figure 9-1. Timer System Block Diagram 9.2 Timer 1 Timer 1 consists of a 16-bit software-programmable counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output compare interrupt. Pulse widths can vary from several microseconds to many seconds. See Figure 9-2. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 77 Timer System INTERNAL BUS INTERNAL PROCESSOR CLOCK HIGH BYTE LOW BYTE 8-BIT BUFFER HIGH BYTE LOW BYTE $16 $17 OUTPUT COMPARE REGISTER /4 HIGH BYTE 16-BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER LOW BYTE $18 $19 INPUT CAPTURE REGISTER $14 $15 $1A $1B OUTPUT COMPARE CIRCUIT OVERFLOW DETECT CIRCUIT EDGE DETECT CIRCUIT TIMER STATUS REGULAR ICF OCF TOF $13 OUTPUT LEVEL REGULAR TIMER CONTROL REGULAR $12 D Q CLK C RESET ICIE OCIE TOIE IEDG OLVL INTERRUPT CIRCUIT (TCMP) OUTPUT LEVEL (NOT CONNECTED TO A PIN) EDGE INPUT (TCAP) Figure 9-2. Timer 1 Block Diagram Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. These registers contain the high byte and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is accessed also. NOTE The I bit in the condition code register (CCR) should be set while manipulating both the high byte and low byte register of a specific timer function to ensure that an interrupt does not occur. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 78 Freescale Semiconductor Timer 1 9.2.1 Counter The key element in the programmable timer is a 16-bit, free-running counter or counter register preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations: $18-$19 (counter register) or $1A-$1B (counter alternate register). A read from only the least significant byte (LSB) of the free-running counter ($19, $1B) receives the count value at the time of the read. If a read of the free-running counter or counter alternate register first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be read to complete the sequence. The counter alternate register differs from the counter register in one respect: A read of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. The free-running counter is configured to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator startup delay. Because the free-running counter is 16 bits preceded by a fixed divided-by-4 prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt also can be enabled when counter roll over occurs by setting its interrupt enable bit (TOIE). 9.2.2 Output Compare Register The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. The output compare register contents are compared with the contents of the free-running counter continually, and if a match is found, the corresponding output compare flag (OCF) bit is set. The output compare register values should be changed after each successful comparison to establish a new elapsed timeout. An interrupt also can accompany a successful output compare, provided the corresponding interrupt enable bit (OCIE) is set. After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) also is written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 79 Timer System 9.2.3 Input Capture Register Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the timer used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. NOTE Since the TCAP pin is shared with the PC3 I/O pin, changing the state of the PC3 DDR or data register can cause an unwanted TCAP interrupt. This can be handled by clearing the ICIE bit before changing the configuration of PC3 and clearing any pending interrupts before enabling ICIE. 9.2.4 Timer Control Register The TCR is a read/write register containing five control bits. Three bits enable interrupts associated with the timer status register flags ICF, OCF, and TOF. Address: Read: Write: Reset: $0012 Bit 7 ICIE 0 U = Unaffected 6 OC1IE 0 5 TOIE 0 4 0 0 3 0 0 2 0 0 1 IEDG U Bit 0 OLVL 0 Figure 9-3. Timer Control Register (TCR) ICIE -- Input Capture Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled OC1IE -- Output Compare 1 Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled TOIE -- Timer Overflow Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 80 Freescale Semiconductor Timer 1 IEDG -- Input Edge The value of the input edge determines which level transition on the TCAP pin will trigger free-running counter transfer to the input capture register. Reset does not affect the IEDG bit. 0 = Negative edge 1 = Positive edge Bits 2-4 -- Not Used Always read logic 0 OLVL -- Not Used Always read logic 0 9.2.5 Timer Status Register The TSR is a read-only register containing three status flag bits. Address: Read: Write: Reset: U U = Unimplemented U 0 U = Unaffected 0 0 0 0 $0013 Bit 7 ICF 6 OC1F 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0 Figure 9-4. Timer Status Register (TSR) ICF -- Input Capture Flag 0 = Flag cleared when TSR and input capture low register ($15) are accessed 1 = Flag set when selected polarity edge is sensed by input capture edge detector OC1F -- Output Compare 1 Flag 0 = Flag cleared when TSR and output compare low register ($17) are accessed 1 = Flag set when output compare register contents match the free-running counter contents TOF -- Timer Overflow Flag 0 = Flag cleared when TSR and counter low register ($19) are accessed 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs Bits 0-4 -- Not Used Always read logic 0 Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit. A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set. 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag. The counter alternate register at address $1A and $1B contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 81 Timer System 9.2.6 Timer During Wait Mode The CPU clock halts during wait mode, but timer 1 remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. 9.2.7 Timer During Stop Mode In stop mode, timer 1 stops counting and holds the last count value if STOP is exited by an interrupt. If RESET is used, the counter is forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake up the MCU. When the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during stop mode. If RESET is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. 9.3 Timer 2 Timer 2 is an 8-bit event counter which has one compare register, one event input pin (EVI), and one event output pin (EVO). The event counter is clocked by the external clock (EXCLK) or prescaled system clock (CLK2), selected by the T2CLK bit in the TCR2 register. The EXCLK may be EVI direct or EVI gated by CLK2, which is selected by the IM2 bit at the EVI block (see 9.3.6 Timer Input 2 (EVI)). Timer 2 may be used as a modulus clock divider with EVO pin, free-running counter (when compare register is $00), or periodic interrupt timer. The timer counter 2 (TCNT2) is an 8-bit up counter with preset input. The counter is preset to $01 by a CMP2 signal from the comparator or by a CPU write to it that is done while the system clock (PH2) is low. COUNTER WRITE CLK2 0 $01 S E COUNTER 2 L $01 EXCLK 1 T2CLK COMPARATOR 2 BUFFER 2 TRANSFER TRANSFER CMP2 REGISTER (OC2) Figure 9-5. Timer 2 Block Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 82 Freescale Semiconductor Timer 2 OC2 = 2, 3, 4 . . . FF, 0 COUNT UP COMPARE PH2 COUNT UP COUNT UP TIMCLK PRESET COUNTER2 N 01 OC2 (BUFFER) N CMP2 EVO OC2 = 1 COUNT UP COMPARE PH2 COUNT UP COUNT UP TIMCLK PRESET COUNTER2 01 PRESET 01 PRESET OC2 (BUFFER) 01 CMP2 EVO Figure 9-6. Timer 2 Timing Diagram for f(PH2) > f(TIMCLK) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 83 Timer System OC2 = 2, 3, 4 . . . FF, 0 1 2 PH2 1 2 1 2 1 2 TIMCLK 3 COUNTER2 N-1 N 01 02 OC2 (BUFFER) N CMP2 EVO Legend: COUNT UP COMPARE PRESET that overrides COUNT UP OC2 = 1 1 2 1 2 1 2 1 2 PH2 TIMCLK 3 COUNTER2 01 3 01 3 01 3 01 OC2 (BUFFER) 01 CMP2 EVO Legend: COUNT UP COMPARE PRESET that overrides COUNT UP Figure 9-7. Timer 2 Timing Diagram for f(PH2) = f(TIMCLK) MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 84 Freescale Semiconductor Timer 2 The CLK2 from the prescaler or the EXTCLK from the EVI block is selected as timer clock by the T2CLK bit in the TCR2 register. The CLK2 and the EXCLK are synchronized to the falling edge of system clock in the prescaler and the EVI blocks. The minimum pulse width of CLK2 is the same as the system clock, and the minimum pulse width of EXCLK (event mode) is one PH2 cycle. When the EXCLK (event mode) is selected, 50% duty is not guaranteed. The counter is incremented by the falling edge of the timer clock and the period between two falling edges is defined as one timer cycle in the following description. The compare register (OC2) is provided for comparison with the timer counter 2 (TCNT2). The OC2 data is transferred to the buffer register when the counter is preset by a CPU write or by a compare output (CMP2). This buffer register is compared with the timer counter 2 (TCNT2). The comparison between the counter and the OC2 buffer register is done when the system clock is high in each bus cycle. If the counter matches with the OC2 buffer register, the comparator latches this result during the current timer cycle. When the next timer cycle begins, the comparator outputs CMP2 signal (if the compare match is detected during previous timer cycle). This CMP2 is used in the counter preset data transfer to the buffer register, setting OC2F in the TSR2 and the EVO block. The counter preset overrides the counter increment. The OC2F bit may generate interrupt requests if the OC2IE bit in the TCR2 is set. 9.3.1 Timer Control Register 2 Address: Read: Write: Reset: $001C BIt 7 TI2IE 0 6 OC2IE 0 5 0 0 4 T2CLK 0 3 IM2 0 2 IL2 0 1 OE2 0 Bit 0 OL2 0 Figure 9-8. Timer Control Register 2 (TCR2) TI2IE -- Timer Input 2 Interrupt Enable The TI2IE bit enables timer input 2 (EVI) interrupt when TI2F is set. This bit is cleared on reset. 0 = Timer input 2 interrupt disabled 1 = Timer input 2 interrupt enabled OC2IE -- Compare 2 Interrupt Enable The OC2IE bit enables compare 2 (CMP2) interrupt when compare match is detected (OC2F is set). This bit is cleared on reset. 0 = Timer input 2 interrupt disabled 1 = Timer input 2 interrupt enabled Bit 5 -- Reserved This bit is not used and is always read as logic 0. T2CLK -- Timer 2 Clock Select The T2CLK bit selects the clock source for the timer counter 2. This bit is cleared on reset. 0 = CLK2 from prescaler selected 1 = EXCLK from EVI input block selected MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 85 Timer System IM2 -- Timer Input 2 Mode Select The IM2 bit selects whether EVI input is gated or not gated by CLK2. This bit is cleared on reset. 0 = EVI not gated by CLK2 (event mode) 1 = EVI gated by CLK2 (gate mode) IL2 -- Timer Input 2 Active Edge (Level) Select The IL2 bit selects the active edge of EVI to increment the counter for event mode (IM2 = 0) or gate enable level of EVI for gate mode (IM2 = 1). This bit is cleared on reset. 0 = Falling edge selected (event mode) Low level enables counting (gate mode) 1 = Rising edge selected (event mode) High level enables counting (gate mode) Table 9-1. EVI Modes Selection IM2 0 0 1 1 IL2 0 1 0 1 Action on Clock Falling edge of EVI increments counter Rising edge of EVI increments counter Low level on EVI enables counting High level on EVI enables counting OE2 -- Timer Output 2 (EVO) Output Enable The OE2 bit enables EVO output on the PC5 pin. When this bit is changed, control of the pin is delayed (synchronized) until the next active edge of EVO is selected by the OL2 bit. This bit is cleared on reset. 0 = EVO output disabled 1 = EVO output enabled OL2 -- Timer Output 2 Edge Select for Synchronization The OL2 bit selects which edge of EVO clock should be synchronized by the OE2 bit control. The OL2 bit also decides the initial value of the CMP2 divider, when counter 2 is written to by the CPU. This bit is cleared on reset. 0 = The falling edge of EVO switches EVO output and PC5 if the OE2 bit has been changed. 1 = The rising edge of EVO switches EVO output and PC5 if the OE2 bit has been changed. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 86 Freescale Semiconductor Timer 2 9.3.2 Timer Status Register 2 Address: Read: Write: Reset: 0 0 $001D BIt 7 TI2F 6 OC2F 5 0 0 4 0 0 3 0 RTI2F 0 2 0 ROC2F 0 1 0 0 Bit 0 0 0 = Unimplemented Figure 9-9. Timer Status Register 2 (TSR2) TI2F -- Timer Input 2 (EVI) Interrupt Flag In event mode, the event edge sets TI2F. In gated time accumulation mode, the trailing edge of the gate signal at the EVI input pin sets TI2F. When the TI2IE bit and this bit are set, an interrupt is generated. This bit is a read-only bit and writes have no effect. The TI2F is cleared by writing a logic 1 to the RTI2F bit and on reset. OC2F -- Compare 2 Interrupt Flag The OC2F bit is set when compare match is detected between counter 2 and OC2 register. When OC2IE bit and this bit are set, an interrupt is generated. This bit is a read-only bit and writes have no effect. The OC2F is cleared by writing a logic 1 to ROC2F bit and on reset. Bits 5 and 4 -- Reserved These bits are not used and always read as logic 0. RTI2F -- Reset Timer Input 2 Flag The RTI2F bit is a write-only bit and always reads as logic 0. Writing logic 1 to this bit clears the TI2F bit and writing a logic 0 to this bit has no effect. ROC2F -- Reset Output Compare 2 Flag The ROC2F bit is a write-only bit and always reads as logic 0. Writing logic 1 to this bit clears the OC2F bit and writing a logic 0 to this bit has no effect. Bits 1 and 0 -- Reserved These bits are not used and always read as logic 0. 9.3.3 Output Compare Register 2 Address: Read: Write: Reset: $001E BIt 7 BIT 7 0 6 BIT 6 0 5 BIT 5 0 4 BIT 4 0 3 BIT 3 0 2 BIT 2 0 1 BIT 1 0 Bit 0 BIT 0 0 Figure 9-10. Output Compare Register 2 (OC2) The OC2 register data is transferred to the buffer register when the CPU writes to TCNT2, when the CMP2 presets the TCNT2, or when system resets. When the OC2 buffer register matches the TCNT2 register, the OC2F bit in the TSR2 register is set and TCNT2 is preset to $01. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 87 Timer System 9.3.4 Timer Counter Register 2 Address: Read: Write: Reset: $001F BIt 7 BIT 7 0 6 BIT 6 0 5 BIT 5 0 4 BIT 4 0 3 BIT 3 0 2 BIT 2 0 1 BIT 1 0 Bit 0 BIT 0 1 Figure 9-11. Timer Counter Register 2 (TCNT2) TCNT2 is incremented by the falling edge of the timer clock, which is synchronized and has the same timing as the falling edge of PH2. The TCNT2 register is compared with the OC2 buffer register and initialized to $01 if it matches. It is also initialized to $01 on reset and any CPU write to this register. The CPU read of this counter should be done while PH2 is high. Data may be latched by the local or main data bus while PH2 is low. 9.3.5 Timebase Control Register 1 Address: Read: Write: Reset: $0010 BIt 7 TBCLK 0 6 0 0 5 LCLK 0 4 0 0 3 0 0 2 0 0 1 T2R1 0 Bit 0 T2R0 0 Figure 9-12. Timebase Control Register 1 (TBCR1) T2R1/T2R0 -- Prescale Rate Select Bits for Timer 2 The T2R1 and T2R0 bits select prescale rate of CLK2 for timer 2 and timer input 2. These bits are cleared on reset. Table 9-2. Timebase Prescale Rate Selection T2R1 0 0 1 1 T2R0 0 1 0 1 System Clock Divided by 1 4 32 256 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 88 Freescale Semiconductor Timer 2 9.3.6 Timer Input 2 (EVI) The event input (EVI) is used as an external clock input for timer 2. TO TI2F PC4 EVI SYNC ACTIVE EDGE/LEVEL SELECTOR GATE/EVENT MODE CONTROL EXCLK PC4 PH2 IL2 IM2 CLK2 Figure 9-13. EVI Block Diagram Since the external clock may be asynchronous to the internal clock, this input has a synchronizer which samples external clock by the internal system clock. (The input transition synchronizes to the falling edge of PH2. Therefore, to be measured, the minimum pulse width for EVI must be larger than one system clock.) The IM2 and IL2 bits in the TCR2 determine how this synchronized external clock is used. The IM2 bit decides between event mode and gate mode, and the IL2 bit decides which level or edge is activated. In event mode (IM2 = 0), the external clock drives the timer 2 counter directly and the active edge at the EVI pin is selected by the IL2 bit. When an active edge is detected, the TI2F bit in the TCR2 is set. Table 9-3. EVI Modes Selection IM2 0 0 1 1 IL2 0 1 0 1 Action on Clock Falling edge of EVI increments counter Rising edge of EVI increments counter Low level on EVI enables counting High level on EVI enables counting NOTE Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should always be cleared whenever EVI is used. EVI should not be used when DDRC4 is high. In gate mode (IM2 = 1), the EVI input is gated by CLK2 from the prescaler and gate output drives the timer 2 counter. The IL2 bit decides active level of the external input. When the transition from active level to inactive level is detected, the TI2F bit is set. Changing the IM2 bit may cause an illegal count up of TCNT2, thus presetting TCNT2 after initializing IM2 is required. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 89 Timer System IM2 = 0 Event Mode EVI PH2 EXCLK IL2 = 0 COUNTER X X+1 X+2 EXCLK IL2 = 1 COUNTER X X+1 X+2 IM2 = 1 Gate Mode EVI SYNCHRONIZED CLK2 EXCLK IL2 = 0 COUNTER EXCLK IL2 = 1 COUNTER Figure 9-14. EVI Timing Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 90 Freescale Semiconductor Timer 2 9.3.7 Event Output (EVO) The EVO pin is the clock output pin of timer 2. The compare output from the timer 2 (CMP2) is divided in this block for 50% duty output signal. This 1/2 divider is initialized to the level of the OL2 bit when the timer counter 2 is written to by the CPU (initialized). When the OE2 bit in the timer control register 2 (TCR2) is set, the EVO output is activated, and, when OE2 is cleared, EVO is deactivated. These controls must be done synchronously to the EVO output signal to avoid an incomplete pulse on the pin. The OL2 bit in the TCR2 decides which edge of EVO should be synchronized. When the DDRC5 bit is set or the synchronized output enable is high (clock on), the output buffer at the EVO/PC5 pin is enabled. If the DDRC5 bit is set to 1, the pin state during the idling condition (clock off) depends on the PC5 output data latch. If the DDRC5 bit is cleared, the pin becomes high impedance during clock off. DDRC5 OE2 D Q OL2 C CMP2 1/2 1 SEL 0 PC5 EVO CNTR2 WRITE PC5 (OUT) PC5 (IN) Figure 9-15. EVO Block Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 91 Timer System OL2 = 0 CNTR2 WRITE CMP2 OE2 CMP2/2 EVO PC5 = 0/EVO OL2 = 1 CMP2 OE2 CMP2/2 EVO PC5 = 1/EVO Figure 9-16. EVO Timing Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 92 Freescale Semiconductor Prescaler 9.4 Prescaler The 8-bit prescaler in the timer system divides system clock (PH2) and provides divided clock to each timer and event input. CLK1 for timer 1 is a fixed frequency clock (PH2/PH4). CLK2 for timer 2 is selected by T2R1 and T2R0 bits in the TBCR1, and this clock is also used as the event input for gate mode. The CLK2 transitions must be synchronous to the falling edge of PH2. Table 9-4. Timebase Prescale Rate Selection T2R1 0 0 1 1 T2R0 0 1 0 1 System Clock Divided by 1 4 32 256 RST PH2 8-BIT DIVIDER 1 4 CLK1 FOR TIMER 1 SEL 1111 CLK2 FOR TIMER 2 1432256 T2R1 T2R0 Figure 9-17. Prescaler Block Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 93 Timer System MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 94 Freescale Semiconductor Chapter 10 LCD Driver 10.1 Introduction The liquid crystal display (LCD) driver may be configured with four backplanes (BP) and 39 frontplanes (FP) maximum. The VDD voltage is the highest level of the output waveform and the lower three levels are applied from VLCD1, VLCD2, and VLCD3 inputs. On reset, LCD enable bit (LCDE) in the LCD control register (LCDCR) is cleared (LCD drivers at a disabled state) and all BP pins and FP pins output VDD levels. The LCD clock is generated by the timebase module, and the LCLK bit in the TBCR1 selects the clock frequency. 10.2 LCD Waveform Examples Figure 10-1, Figure 10-2, Figure 10-3, and Figure 10-4 illustrate the LCD timing examples. DUTY = 1/1 (STATIC) BIAS = 1/1 (VLCD1 = VDD, VLCD2 = VLCD3 = VDD-VLCD) 1FRAME BP0 VDD, VLCD1 VLCD2, 3 FPx (XXX1) VDD, VLCD1 VLCD2, 3 FPy (XXX1) VDD, VLCD1 VLCD2, 3 +VLCD BP0-FPx (OFF) 0 -VLCD +VLCD BP0-FPy (ON) 0 -VLCD Figure 10-1. LCD 1/1 Duty and 1/1 Bias Timing Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 95 LCD Driver DUTY = 1/2 BIAS = 1/2 (VLCD1 = VLCD2 = VDD-VLCD/2, VLCD3 = VDD-VLCD) 1 FRAME VDD BP0 VLCD1, 2 VLCD3 VDD BP1 VLCD1, 2 VLCD3 FPX (XX01) VDD VLCD1, 2 VLCD3 FPY (XX00) VDD VLCD1, 2 VLCD3 VLCD VLCD/2 BP0-FPX (ON) 0 -VLCD/2 -VLCD VLCD VLCD/2 BP1-FPX (OFF) 0 -VLCD/2 -VLCD VLCD VLCD/2 BP0-FPY (OFF) 0 -VLCD/2 -VLCD Figure 10-2. LCD 1/2 Duty and 1/2 Bias Timing Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 96 Freescale Semiconductor LCD Waveform Examples DUTY = 1/3 BIAS = 1/3 (VLCD1 = VDD-VLCD/3, VLCD2 = VDD-2VLCD/3, VLCD3 = VDD-VLCD) 1FRAME VDD VLCD1 BP0 VLCD2 VLCD3 VDD BP1 VLCD1 VLCD2 VLCD3 VDD BP2 VLCD1 VLCD2 VLCD3 VDD FPx (X010) VLCD1 VLCD2 VLCD3 +VLCD +2VLCD/3 BP0-FPx (OFF) +VLCD/3 0 -VLCD/3 -2VLCD/3 -VLCD +VLCD +2VLCD/3 +VLCD/3 BP1-FPx (ON) 0 -VLCD/3 -2VLCD/3 -VLCD Figure 10-3. LCD 1/3 Duty and 1/3 Bias Timing Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 97 LCD Driver DUTY = 1/4 BIAS = 1/3 (VLCD1 = VDD-VLCD/3, VLCD2 = VDD-2VLCD/3, VLCD3 = VDD-VLCD) 1FRAME VDD VLCD1 BP0 VLCD2 VLCD3 VDD BP1 VLCD1 VLCD2 VLCD3 VDD BP2 VLCD1 VLCD2 VLCD3 VDD BP3 VLCD1 VLCD2 VLCD3 VDD FPX (1001) VLCD1 VLCD2 VLCD3 +VLCD +2VLCD/3 +VLCD/3 BP0-FPX (ON) 0 -VLCD/3 -2VLCD/3 -VLCD +VLCD +2VLCD/3 +VLCD/3 BP1-FPX (OFF) 0 -VLCD/3 -2VLCD/3 -VLCD Figure 10-4. LCD 1/4 Duty and 1/3 Bias Timing Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 98 Freescale Semiconductor Backplane Driver and Port Selection 10.3 Backplane Driver and Port Selection The number of backplane (port D) pins depends on the LCD duty. It is automatically selected by DUTY1 and DUTY0 bits in the LCD control register (LCDCR). On reset, these bits are cleared and 1/4 duty is selected. (See Table 10-1.) Table 10-1. Backplane and Port Selection Duty 1/1 1/2 1/3 1/4 LCD Control DUTY1 0 1 1 0 DUTY0 1 0 1 0 BP3/PD3 PD3 PD3 PD3 BP3 Pin Selection BP2/PD2 PD2 PD2 BP2 BP2 BP1/PD1 PD1 BP1 BP1 BP1 BP0 BP0 BP0 BP0 BP0 10.4 Frontplane Driver and Port Selection The number of frontplane (FP) pins depends on the number of port D and port E bits. If port bits are selected as a parallel output port, the number of the FP pins is decreased to 27 as a minimum. The selections between frontplane and port (nibble wide) are done by the PEH, PEL, and PDH bits in the LCDCR (see Table 10-2). These bits also can be controlled on a bit-wide basis by using the PDMUX and PEMUX registers. PDH, PEH, and PEL have priority over the mux registers. On reset, port D and port E bits are disconnected and FP27-FP38 pins output VDD levels. Table 10-2. Frontplane and Port Selection FP / Port Control PEH PEL PDH 0 0 1 0 0 1 0 0 1 1 X PDMx 0 1 X 0 1 X 0 1 X FP27:FP30 Varied PE7:PE4 FP31:FP34 Varied PE3:PE0 PEMx FP27:FP30/ PE7:PE4 Port Selection FP31:FP34/ PE3:PE0 FP35:FP38/ PD7:PD4 FP35:FP38 Varied PD7:PD4 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 99 LCD Driver 10.5 LCD Control Register Address: Read: Write: Reset: $0020 Bit 7 LCDE 0 6 DUTY1 0 5 DUTY0 0 4 0 0 3 PEH 0 2 PEL 0 1 PDH 0 Bit 0 0 0 Figure 10-5. LCD Control Register (LCDCR) LCDE -- LCD Output Enable The LCDE bit enables all BP and FP outputs. (This bit does not affect PEH, PEL, or PDH bits.) This bit is cleared on reset. 0 = All dedicated FP pins output highest (VDD) level; BP and FP pins are shared with an output port data. 1 = All BP and FP pins output LCD waveforms. DUTY1 and DUTY0 -- LCD Duty Select The DUTY1 and DUTY0 bits select the duty of the LCD driver. The number of BP pins is related to this duty selection. The unused BP pin is used as a port D pin. Default duty is 1/4 duty. These bits are cleared on reset. See Table 10-1. Bit 4 -- Reserved This bit is not used and always reads as logic 0. PEH -- Select Port E (H) The PEH bit enables the upper four bits of port E instead of LCD drivers. This bit is cleared on reset. See 10.4 Frontplane Driver and Port Selection. 0 = FP27-FP30 selected 1 = PE7-PE4 selected PEL -- Select Port E (L) The PEL bit enables the lower four bits of port E instead of LCD drivers. This bit is cleared on reset. See 10.4 Frontplane Driver and Port Selection. 0 = FP31-FP34 selected 1 = PE3-PE0 selected PDH -- Select Port D (H) The PDH bit enables the upper four bits of port D instead of LCD drivers. This bit is cleared on reset. See 10.4 Frontplane Driver and Port Selection. 0 = FP35-FP38 selected 1 = PD7-PD4 selected Bit 0 -- Reserved This bit is not used and is always read as logic 0. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 100 Freescale Semiconductor LCD Data Register 10.6 LCD Data Register Address: $0021-$0034 FP (2x-1) Bit 7 Read: Write: Reset: BP3 6 BP2 5 BP1 4 BP0 3 BP3 2 BP2 FP (2x-2) 1 BP1 Bit 0 BP0 Unaffected by reset Figure 10-6. LDC Data Registers LCDRx -- LCD Data Registers Data in the LCDRx (LCDR1-LCDR20) controls the waveform of the two frontplane drivers. Bits 0-3 and bits 4-7 of this register decide the waveforms at the BP0-BP3 timings. If the LCD duty is not 1/4, the register bit for the unused backplane has no meaning. The upper four bits of LCDR20 are not implemented and unknown data may be read. (See Table 10-3.) 0 = Output deselect waveform at the corresponding backplane timing 1 = Output select waveform at the corresponding backplane timing Table 10-3. Frontplane Data Register Bit Usage Duty 1/1 1/2 1/3 1/4 Frontplane Data Register Bit Usage Bit 7 -- -- -- BP3 Bit 6 -- -- BP2 BP2 Bit 5 -- BP1 BP1 BP1 Bit 4 BP0 BP0 BP0 BP0 Bit 3 -- -- -- BP3 Bit 2 -- -- BP2 BP2 Bit 1 -- BP1 BP1 BP1 Bit 0 BP0 BP0 BP0 BP0 MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 101 LCD Driver MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 102 Freescale Semiconductor Chapter 11 Instruction Set 11.1 Introduction The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS (complementary metal-oxide semiconductor) Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator. 11.2 Addressing Modes The central processor unit (CPU) uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * Inherent * Immediate * Direct * Extended * Indexed, no offset * Indexed, 8-bit offset * Indexed, 16-bit offset * Relative 11.2.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 11.2.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 11.2.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 103 Instruction Set 11.2.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. 11.2.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used random-access memory (RAM) or input/output (I/O) location. 11.2.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 11.2.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Freescale assembler determines the shortest form of indexed addressing. 11.2.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 104 Freescale Semiconductor Instruction Types 11.3 Instruction Types The MCU instructions fall into these five categories: * Register/memory instructions * Read-modify-write instructions * Jump/branch instructions * Bit manipulation instructions * Control instructions 11.3.1 Register/Memory Instructions These instructions operate on central processor unit (CPU) registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1. Register/Memory Instructions Instruction Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 105 Instruction Set 11.3.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE Do not use read-modify-write operations on write-only registers. Table 11-2. Read-Modify-Write Instructions Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2) 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 106 Freescale Semiconductor Instruction Types 11.3.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 11-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 107 Instruction Set 11.3.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 11-4. Bit Manipulation Instructions Instruction Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set Mnemonic BCLR BRCLR BRSET BSET 11.3.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 11-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 108 Freescale Semiconductor Instruction Set Summary 11.4 Instruction Set Summary Table 11-6. Instruction Set Summary (Sheet 1 of 6) Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel Operation Description H I NZC Add with Carry A (A) + (M) + (C) -- IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL 2 A9 ii B9 dd 3 C9 hh ll 4 D9 ee ff 5 4 E9 ff 3 F9 2 AB ii BB dd 3 CB hh ll 4 DB ee ff 5 4 EB ff 3 FB 2 A4 ii B4 dd 3 C4 hh ll 4 D4 ee ff 5 4 E4 ff 3 F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 2F 2E dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3 3 3 Add without Carry A (A) + (M) -- Logical AND A (A) (M) ---- -- Arithmetic Shift Left (Same as LSL) C b7 b0 0 ---- ff dd Arithmetic Shift Right b7 b0 C ---- ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr Branch if Carry Bit Clear PC (PC) + 2 + rel ? C = 0 ---------- BCLR n opr Clear Bit n Mn 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL REL REL REL REL BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- ---------- ---------- ---------- MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 109 Cycles Effect on CCR Operand Address Mode Instruction Set Table 11-6. Instruction Set Summary (Sheet 2 of 6) Opcode Source Form BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operation Description H I NZC Bit Test Accumulator with Memory Byte (A) (M) ---- -- IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 2 A5 ii B5 dd 3 C5 hh ll 4 D5 ee ff 5 4 E5 ff 3 F5 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1 ---------- PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- ---------- ---------- ---------- ---------- ---------- ---------- BRCLR n opr rel Branch if Bit n Clear PC (PC) + 2 + rel ? Mn = 0 -------- BRN rel Branch Never PC (PC) + 2 + rel ? 1 = 0 ---------- BRSET n opr rel Branch if Bit n Set PC (PC) + 2 + rel ? Mn = 1 -------- BSET n opr Set Bit n Mn 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) BSR rel Branch to Subroutine PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0 ---------- REL AD rr CLC CLI Clear Carry Bit Clear Interrupt Mask -------- 0 -- 0 ------ INH INH 98 9A MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 110 Freescale Semiconductor Cycles 6 2 2 Effect on CCR Operand Address Mode Instruction Set Summary Table 11-6. Instruction Set Summary (Sheet 3 of 6) Opcode Source Form CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Operation Description M $00 A $00 X $00 M $00 M $00 H I NZC Clear Byte ---- 0 1 -- DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX 3F 4F 5F 6F 7F dd ff Compare Accumulator with Memory Byte (A) - (M) ---- 2 A1 ii B1 dd 3 C1 hh ll 4 D1 ee ff 5 4 E1 ff 3 F1 33 43 53 63 73 dd 5 3 3 6 5 Complement Byte (One's Complement) M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M) ---- 1 ff Compare Index Register with Memory Byte (X) - (M) ---- 2 A3 ii B3 dd 3 C3 hh ll 4 D3 ee ff 5 4 E3 ff 3 F3 3A 4A 5A 6A 7A dd 5 3 3 6 5 Decrement Byte M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 ---- -- ff EXCLUSIVE OR Accumulator with Memory Byte A (A) (M) ---- -- 2 A8 ii B8 dd 3 C8 hh ll 4 D8 ee ff 5 4 E8 ff 3 F8 3C 4C 5C 6C 7C dd 5 3 3 6 5 Increment Byte M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 ---- -- ff Unconditional Jump PC Jump Address ---------- BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 BD dd 5 CD hh ll 6 DD ee ff 7 6 ED ff 5 FD Jump to Subroutine PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address ---------- MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 111 Cycles 5 3 3 6 5 Effect on CCR Operand Address Mode Instruction Set Table 11-6. Instruction Set Summary (Sheet 4 of 6) Opcode Source Form LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation Description H I NZC Load Accumulator with Memory Byte A (M) ---- -- IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH 2 A6 ii B6 dd 3 C6 hh ll 4 D6 ee ff 5 4 E6 ff 3 F6 2 AE ii BE dd 3 CE hh ll 4 DE ee ff 5 4 EE ff 3 FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D AA BA CA DA EA FA 39 49 59 69 79 36 46 56 66 76 9C ii dd hh ll ee ff ff dd dd dd 5 3 3 6 5 5 3 3 6 5 1 1 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2 Load Index Register with Memory Byte X (M) ---- -- Logical Shift Left (Same as ASL) C b7 b0 0 ---- ff dd Logical Shift Right 0 b7 b0 C ---- 0 ff Unsigned Multiply X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) 0 ------ 0 Negate Byte (Two's Complement) ---- ff No Operation ---------- Logical OR Accumulator with Memory A (A) (M) ---- -- Rotate Byte Left through Carry Bit C b7 b0 ---- ff dd Rotate Byte Right through Carry Bit b7 b0 C ---- ff Reset Stack Pointer SP $00FF ---------- MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 112 Freescale Semiconductor Cycles Effect on CCR Operand Address Mode Instruction Set Summary Table 11-6. Instruction Set Summary (Sheet 5 of 6) Opcode Source Form Operation Description SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) ---------- H I NZC RTI Return from Interrupt INH 80 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Return from Subroutine INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX 81 Subtract Memory Byte and Carry Bit from Accumulator A (A) - (M) - (C) ---- 2 A2 ii B2 dd 3 C2 hh ll 4 D2 ee ff 5 4 E2 ff 3 F2 99 9B B7 C7 D7 E7 F7 8E BF CF DF EF FF dd hh ll ee ff ff dd hh ll ee ff ff 2 2 4 5 6 5 4 2 4 5 6 5 4 Set Carry Bit Set Interrupt Mask C1 I1 -------- 1 -- 1 ------ Store Accumulator in Memory M (A) ---- -- Stop Oscillator and Enable IRQ Pin -- 0 ------ Store Index Register In Memory M (X) ---- -- Subtract Memory Byte from Accumulator A (A) - (M) ---- 2 A0 ii B0 dd 3 C0 hh ll 4 D0 ee ff 5 4 E0 ff 3 F0 SWI Software Interrupt PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ---------- INH 83 TAX TST opr TSTA TSTX TST opr,X TST ,X Transfer Accumulator to Index Register INH DIR INH INH IX1 IX 97 3D 4D 5D 6D 7D dd Test Memory Byte for Negative or Zero (M) - $00 ---- -- ff MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 113 Cycles 9 6 1 0 2 4 3 3 5 4 Effect on CCR Operand Address Mode Instruction Set Table 11-6. Instruction Set Summary (Sheet 6 of 6) Opcode Source Form TXA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n Operation Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Description A (X) H I NZC ---------- -- 0 ------ opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : -- INH INH 9F 8F Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected 11.5 Opcode Map See Table 11-7. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 114 Freescale Semiconductor Cycles 2 2 Effect on CCR Operand Address Mode Freescale Semiconductor MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 115 Table 11-7. Opcode Map Bit Manipulation DIR DIR MSB LSB Branch REL 2 DIR 3 Read-Modify-Write INH INH IX1 4 5 6 IX 7 Control INH INH 8 9 RTI INH 6 RTS INH IMM A 2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2 DIR B Register/Memory EXT IX2 C 4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3 IX1 E 4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1 IX F 3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX MSB LSB 0 1 9 D 5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2 0 1 2 3 4 5 6 7 8 9 A B C D E F 5 5 3 5 3 3 6 5 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BCLR0 BRN 3 DIR 2 DIR 2 REL 1 5 5 3 11 BRSET1 BSET1 BHI MUL 3 DIR 2 DIR 2 REL 1 INH 5 5 3 5 3 3 6 5 BRCLR1 BCLR1 BLS COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BCLR5 BMI 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BSET6 BMC INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BSET7 BIL 3 DIR 2 DIR 2 REL 1 5 5 3 5 3 3 6 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 2 2 2 10 SWI INH 2 2 2 2 1 1 1 1 1 1 1 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2 2 STOP INH 2 2 WAIT TXA INH 1 INH 6 BSR REL 2 2 LDX 2 IMM 2 2 MSB LSB 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 0 1 2 3 4 5 6 7 8 9 A B C D E F INH = Inherent IMM = Immediate DIR = Direct EXT = Extended REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset 0 MSB of Opcode in Hexadecimal Opcode Map LSB of Opcode in Hexadecimal 0 5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode Instruction Set MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 116 Freescale Semiconductor Chapter 12 Electrical Specifications 12.1 Introduction This section contains parametric and timing information. 12.2 Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. Keep VIn and VOut within the range VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. Rating Symbol VDD VLCD1 VLCD2 VLCD3 VIn VIn VOut I TJ Tstg Value -0.3 to +7.0 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD + 0.3 VSS -0.3 to 2 x VDD + 0.3 VSS -0.3 to VDD + 0.3 12.5 +150 -55 to +150 Unit Supply voltage V Input voltage Self-check mode (IRQ1 pin only) Output voltage Current drain per pin excluding VDD and VSS Operating junction temperature Storage temperature range V V V mA C C NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 12.6 5.0-Volt DC Electrical Characteristics and 12.7 3.3-Volt DC Electrical Characteristics for guaranteed operating conditions. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 117 Electrical Specifications 12.3 Operating Temperature Range Characteristic Operating temperature range MC68HC05L16 (standard) MC68HC05L16C (extended) Symbol TA Value TL to TH 0 to +70 -40 to +85 Unit C 12.4 Thermal Characteristics Characteristic Thermal resistance 80-pin plastic quad flat pack Symbol JA Value 120 Unit C/W 12.5 Recommended Operating Conditions Rating(1) (fOP = 2.1 MHz) (fOP = 1.0 MHz) Supply voltage Symbol VDD VDD VLCD1 VLCD2 VLCD3 Fast clock oscillation frequency External capacitance (fOSC = 3.52 MHz) Slow clock oscillation frequency External capacitance (fXOSC = 32.768 kHz) fOSC C1 C2 fXOSC CX1 CX2 -- -- -- -- -- -- Min 4.5 2.2 Typ 5.0 -- VDD - 1/3 VLCD VDD - 2/3 VLCD VDD - 3/3 VLCD 3.52 33 33 32.768 18 22 4.2 -- -- -- -- -- Max 5.5 5.5 Unit V V V V V MHz pF MHz pF 1. +2.2 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 118 Freescale Semiconductor 5.0-Volt DC Electrical Characteristics 12.6 5.0-Volt DC Electrical Characteristics Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 5.0 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Output low voltage (VDD = 5.0 V) (ILoad = 0.8 mA) PA0-PA7, PC0-PC7, PD1-PD7, PE0-PE7 Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fop = 2.1 MHz) Wait (fop = 2.1 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 5.0 V, TA = +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 5.0 V) PA0-PA7 PB0-PB7 PC0-PC5 PC6-PC7 LCD pin output impedance FP0-FP26 BP0-BP3 Symbol VOL VOH VOH Min -- VDD -0.1 VDD -0.8 Typ Max Unit -- -- 0.1 -- V -- -- V VOL VIH VIL -- 0.7 x VDD VSS -- -- -- 0.4 VDD 0.3 x VDD V V V IDD -- -- -- -- 6.0 3.0 3.0 17.0 -- 12.0 6.0 10.0 -- 1.0 mA mA A A A IIn -- IIn 50 50 200 30 -- -- 180 180 700 125 10 5 400 400 1400 300 20 18 A A A A k k Zo, FP Zo, BP 1. +4.5 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 4.2 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current is measured with output transistor turned off and VIn = 0 V. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 119 Electrical Specifications 12.7 3.3-Volt DC Electrical Characteristics Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 3.5 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Output low voltage (VDD = 3.5 V) (ILoad = 0.8 mA) PA0-PA7, PC0-PC7, PD1-PD7, PE0-PE7 Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET,OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fop = 1.0 MHz) Wait (fop = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 3.0 V, TA= +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 3.3 V) PA0-PA7 PB0-PB7 PC0-PC5 PC6-PC7 LCD pin output impedance FP0-FP26 BP0-BP3 Symbol VOL VOH VOH VOL VIH VIL Min -- VDD -0.1 VDD -0.8 -- 0.7 x VDD VSS Typ Max Unit -- -- -- 0.1 -- -- V V -- -- -- 0.4 VDD 0.3 x VDD V V V IDD -- -- -- -- 1.8 0.8 2.0 8.0 -- 4.0 2.0 10.0 -- 1.0 mA mA A A A IIn -- IIn 20 20 50 30 -- -- 75 75 300 100 10 5 300 300 1000 250 20 18 A A A A k k Zo, FP Zo, BP 1. +3.0 VDD < +4.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current is measured with output transistor turned off and VIn = 0 V. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 120 Freescale Semiconductor 2.7-Volt DC Electrical Characteristics 12.8 2.7-Volt DC Electrical Characteristics Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 2.2 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Output low voltage (VDD = 2.2 V) (ILoad = 0.4 mA) PA0-PA7, PC0-PC7, PD1-PD7, PE0-PE7 Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fop = 1.0 MHz) Wait (fop = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 2.2 V, TA= +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 2.7 V) PA0-PA7 PB0-PB7 PC0-PC5 PC6-PC7 LCD pin output impedance FP0-FP26 BP0-BP3 Symbol VOL VOH VOH VOL VIH VIL Min -- VDD -0.1 VDD -0.6 -- 0.7 x VDD VSS Typ Max Unit -- -- -- 0.1 -- -- V V -- -- -- 0.3 VDD 0.3 x VDD V V V -- -- IDD -- -- IIn -- 0.7 0.4 1.5 5.0 -- 2.2 1.4 10.0 -- 1.0 mA mA A A A IIn 5 5 30 20 -- -- 50 50 200 85 10 5 150 150 600 200 20 18 A A A A k k Zo, FP Zo, BP 1. +2.2 VDD < +3.0 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current is measured with output transistor turned off and VIn = 0 V. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 121 Electrical Specifications 12.9 Control Timing Characteristic(1) Frequency of oscillation (OSC) Crystal External clock Internal operating frequency(2), crystal or external clock (fOSC/2) VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V Cycle time (fast OSC selected) VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V RESET pulse width when bus clock active Timer Resolution Input capture (TCAP) pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period(3) OSC1 pulse width (external clock input) Symbol fosc Min -- dc Max 4.2 4.2 Unit MHz fop -- -- 2.1 1.0 MHz tcyc tRL tRESL tTH, tTL tILIH tILIL tOH, tOL 480 1.0 1.5 4.0 284 284 see note 110 -- -- -- -- -- -- -- -- ns s tcyc tcyc ns ns tcyc ns 1. +2.2 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. 2. The system clock divider configuration (SYS1-SYS0 bits) should be selected such that the internal operating frequency (fOP) does not exceed value specified in fOP for a given fOSC. 3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 122 Freescale Semiconductor Control Timing OSC1 1 t RESET RL t IRQ 2 ILIH t IRQ3 ILCH 8092 t cyc INTERNAL CLOCK INTERNAL ADDRESS BUS FFFE FFFE FFFE FFFE FFFF4 Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option 4. RESET vector address shown for timing example RESET OR INTERRUPT VECTOR FETCH Figure 12-1. Stop Recovery Timing Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 123 Electrical Specifications MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 124 Freescale Semiconductor Chapter 13 Mechanical Specifications 13.1 Introduction This section describes the dimensions of the quad flat pack (QFP). MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 125 Mechanical Specifications 13.2 Quad Flat Pack (QFP) -- Case 841B-01 L 60 61 41 40 S S D D B B S S -AL -BB 0.20 (0.008) M C A-B 0.05 (0.002) A-B V 0.20 (0.008) M H A-B P -A,B,DDETAIL A DETAIL A 80 1 20 21 F -DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B 0.20 (0.008) M S D S S H A-B J S N D S E C -CSEATING PLANE M DETAIL C DATUM PLANE D 0.20 (0.008) M C A-B S D S SECTION B-B -HH M G 0.01 (0.004) U T DATUM PLANE -H- R K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A , B AND D TO BE DETERMINED AT DATUM PLANE H . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 14.10 13.90 14.10 13.90 2.45 2.15 0.38 0.22 2.40 2.00 0.33 0.22 0.65 BSC 0.25 0.23 0.13 0.95 0.65 12.35 BSC 10 5 0.17 0.13 0.325 BSC 7 0 0.30 0.13 17.45 16.95 0.13 0 17.45 16.95 0.45 0.35 1.6 REF INCHES MIN MAX 0.547 0.555 0.547 0.555 0.084 0.096 0.009 0.015 0.079 0.094 0.009 0.013 0.026 BSC 0.010 0.005 0.009 0.026 0.037 0.486 BSC 10 5 0.005 0.007 0.013 BSC 7 0 0.005 0.012 0.667 0.687 0.005 0 0.667 0.687 0.014 0.018 0.06 REF MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 126 Freescale Semiconductor Chapter 14 Ordering Information 14.1 Introduction This section contains instructions for ordering custom-masked ROM MCUs. 14.2 MCU Ordering Forms To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Freescale representative. Submit the following items when ordering MCUs: * A current MCU ordering form that is completely filled out (Contact your Freescale sales office for assistance.) * A copy of the customer specification if the customer specification deviates from the Freescale specification for the MCU * Customer's application program on one of the media listed in 14.3 Application Program Media 14.3 Application Program Media Please deliver the application program to Freescale in one of the following media: * Macintosh(R)(1) 3 1/2-inch diskette (double-sided 800 K or double-sided high-density 1.4 M) * MS-DOS(R)(2) or PC-DOSTM(3) 3 1/2-inch diskette (double-sided 720 K or double-sided high-density 1.44 M) * MS-DOS(R) or PC-DOSTM 5 1/4-inch diskette (double-sided double-density 360 K or double-sided high-density 1.2 M) Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with the following information: * Customer name * Customer part number * Project or product name * File name of object code * Date * Name of operating system that formatted diskette * Formatted capacity of diskette 1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 127 Ordering Information On diskettes, the application program must be in Freescale's S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. NOTE Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering form for additional requirements. Freescale may request pattern re-submission if non-user areas contain any non-zero code. If the memory map has two user ROM areas with the same addresses, then write the two areas in separate files on the diskette. Label the diskette with both filenames. In addition to the object code, a file containing the source code can be included. Freescale keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the filename of the source code. 14.4 ROM Program Verification The primary use for the on-chip ROM is to hold the customer's application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Freescale inputs the customer's application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain non-user ROM code, such as self-check code. Freescale sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Freescale will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Freescale. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask. 14.5 ROM Verification Units (RVUs) After receiving the signed listing verify form, Freescale manufactures a custom photographic mask. The mask contains the customer's application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Freescale then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer's user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Freescale Quality Assurance. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 128 Freescale Semiconductor MC Order Numbers 14.6 MC Order Numbers Table 14-1 shows the MC order numbers for the available package types. Table 14-1. MC Order Numbers Package Type 80-pin plastic quad flat pack (QFP) Operating Temperature Range 0C to +70C -40C to +85C MC Order Number MC68HC05L16FU MC68HC05L16CFU MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 129 Ordering Information MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 130 Freescale Semiconductor Appendix A MC68HC705L16 A.1 Introduction The MC68HC705L16 is similar to the MC68HC05L16 with the exception of the EPROM feature. The program ROM on the MC68HC05L16 has been replaced by 16-K electrically programmable read-only memory to allow modification of the program code for emulation. The entire data sheet of the MC68HC05L16 applies to the EPROM part with the additions and exceptions explained in this appendix. The additional features available on the MC68HC705L16 are: * 16,384 bytes of EPROM * On-chip bootstrap firmware for programming use * Self-check mode replaced by bootstrap capability A.2 Differences between MC68HC05L16 and MC68HC705L16 Table A-1. Differences Between MC68HC05L16 and MC68HC705L16 Item ROM memory type Internal test mode LCD 1/2 duty 1/2 bias waveform EPROM programming Mask option OSC, XOSC, and RESET pin resistor option MC68HC05L16 Mask ROM Self-check mode See Figure 10-2 Not applicable Customer specified Available by mask option MC68HC705L16 EPROM Bootstrap mode See Figure A-6 Through VPP pin and PCR No mask option Not available A.3 MCU Structure Figure A-1 shows the structure of the MC68HC705L16 MCU. A.4 Mask Options There are no mask options available for the MC68HC705L16. For this reason, the address option map shown in Chapter 2 Memory Map has no meaning. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 131 MC68HC705L16 OSC1 OSC2 XOSC1 XOSC2 OSC DIV SEL XOSC INTERNAL PROCESSOR CLOCK TIMEBASE SYSTEM PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 KEY WAKEUP DATA B DIR REG PORT B DATA A DIR REG /2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 SRAM 512 BYTES BOOTSTRAP ROM SPI 496 BYTES COP SYSTEM PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6*/IRQ2 PC7*/IRQ1 DATA C DIR REG EPROM 16,384 BYTES + 16 BYTES RESET CPU CONTROL M68HC05 CPU ALU V CPU REGISTERS DD SS ACCUMULATOR INDEX REGISTER TIMER2 LCD DRIVERS PORT C PORT A FP0-PF26 V V PP ** PROGRAM COUNTER CONDITION CODE REG PORT E STACK POINTER FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 BP3/PD3 BP2/PD2 BP1/PD1 BP0 VLCD3 VLCD2 VLCD1 * Open drain only when output ** The VPP pin should be connected to VDD in single-chip Figure A-1. Block Diagram NOTE A line over a signal name indicates an active low signal. For example, RESET is active low. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 132 Freescale Semiconductor PORT D Functional Pin Description A.5 Functional Pin Description The MC68HC705L16 is available in the 80-pin quad flat pack (QFP). The pin assignment is shown in Figure A-2. FP27/PE7 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 80 VDD FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 VLCD3 VLCD2 VLCD1 VSS VPP** XOSC1 XOSC2 RESET 1 61 60 VSS FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1/PD1 BP2/PD2 BP3/PD3 VDD PC7*/IRQ1 PC6*/IRQ2 PC5/EVO PC4/EVI PC3/TCAP PC2/SCK 20 21 40 41 * Open drain only when output **The VPP pin should be connect to VDD in single-chip mode. Figure A-2. Pin Assignments for Single-Chip Mode A.6 Programming Voltage (VPP) In single-chip (user) mode, the VPP pin should be tied to VDD level. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 133 OSC1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO MC68HC705L16 Table A-2. Pin Configuration Pin Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 17 47 1 60 16 21 22 18 19 15 14 13 48 49 50 51 SCM, Bootstrap PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6*/IRQ2 PC7*/IRQ1 VPP** VDD VDD VSS VSS OSC1 OSC2 XOSC1 XOSC2 VLCD1 VLCD2 VLCD3 BP3/PD3 BP2/PD2 BP1/PD1 BP0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I/O I/O I/O I/O I/O I/O I I I I I O O I O I O I I I O O O O Pin Number 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 SCM, Bootstrap FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O *Open drain only when output **The VPP pin should be connect to VDD in single-chip mode. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 134 Freescale Semiconductor Modes of Operation A.7 Modes of Operation The MC68HC705L16 has the following operating modes: single-chip mode (SCM) and bootstrap mode. Single-chip mode, also called user mode, allows maximum use of pins for on-chip peripheral functions. The bootstrap mode is provided for EPROM programming, dumping EPROM contents, and loading programs into the internal RAM and executing them. This is a versatile mode because there are essentially no limitations on the special-purpose program that is boot-loaded into the internal RAM. A.7.1 Mode Entry Mode entry is done at the rising edge of the RESET pin. Once the device enters one of the modes, the mode cannot be changed by software. Only an external reset can change the mode. At the rising edge of the RESET pin, the device latches the states of IRQ1 and IRQ2 and places itself in the specified mode. While the RESET pin is low, all pins are configured as single-chip mode. Table A-3 shows the states of IRQ1 and IRQ2 for each mode entry. High voltage VTST = 2 x VDD is required to select modes other than single-chip mode. Table A-3. Mode Select Summary Modes Single-chip (user) mode Bootstrap mode RESET PC6/IRQ1 VSS or VDD VTST PC7/IRQ2 VSS or VDD VDD SINGLE-CHIP MODE RESET VDD VSS VTST IRQ1 VDD VSS IRQ2 VTST = 2 x VDD VDD VSS Figure A-3. Mode Entry Diagram A.7.2 Single-Chip Mode (SCM) In this mode, all address and data bus activity occurs within the MCU. Thus, no external pins are required for these functions. The single-chip mode allows the maximum number of I/O pins for on-chip peripheral functions, for example, ports A through E, and LCD drivers. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 135 MC68HC705L16 A.7.3 Bootstrap Mode In this mode, the reset vector is fetched from a 496-byte internal bootstrap ROM at $FE00-$FFEF. The bootstrap ROM contains a small program which loads a program into the internal RAM and then passes control to that program at location $0040 or executes the EPROM programming sequence and dumps EPROM contents. Since these modes are not normal user modes, all of the privileged control bits are accessible. This allows the bootstrap mode to be used for self test of the device. A.8 Memory Map The MC68HC705L16 contains a 16,384-byte EPROM, 496 bytes of bootstrap ROM, and 512 bytes of RAM. An additional 16 bytes of EPROM are provided for user vectors at $FFF0-$FFFF. The MCU's memory map is shown in Figure A-4. $0000 I/O 64 BYTES $003F $0040 RAM 512 BYTES $00C0 $00FF $023F $0240 UNUSED $0FFF $1000 EPROM 16 KBYTES $4FFF $5000 UNUSED $FDFF $FE00 BOOTSTRAP ROM 496 BYTES $FFDF $FFE0 $FFEF $FFF0 $FFFF STACK 64 BYTES 0 $0000 DUAL-MAPPED I/O REGISTERS 16 BYTES $000F $0010 0000 63 64 191 192 255 256 575 576 0015 0016 I/O 48 BYTES 4095 4096 $003F 0063 20479 20480 65023 65024 TEST VECTORS USER VECTORS 65503 65504 65519 65520 65535 Figure A-4. Memory Map MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 136 Freescale Semiconductor Boot ROM A.9 Boot ROM Boot ROM is 496 bytes of mask ROM positioned at $FE00-$FFEF. This ROM contains bootstrap loader programs and reset/interrupt vectors in the bootstrap mode. The bootstrap loader programs include: * EPROM programming and verification * Dumping EPROM contents * Loading programs into the internal RAM * Executing programs in the internal RAM A.10 EPROM The 16-Kbyte EPROM is positioned at $1000-$4FFF, and the additional 16 bytes of EPROM are located at $FFF0-$FFFF for user vectors. The erased state of EPROM is read as $FF and EPROM power is supplied from the VPP pin and the VDD pin. The program control register (PCR) is provided for EPROM programming and testing. The functions of EPROM depend on the device mode. In user mode, ELAT and PGM bits in the PCR are available for user programming, and the remaining test bits become read-only bits. The VPP pin should be tied to 5 volts or programming voltage. A.10.1 Programming Sequence To program the MC68HC705L16, execute this sequence: * Set the ELAT bit * Write the data to the address to be programmed * Set the PGM bit * Delay for an appropriate amount of time * Clear the PGM bit and the ELAT bit Clearing the PGM bit and the ELAT bit may be done on a single CPU write. NOTE It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should be equal to VDD during normal operations. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 137 MC68HC705L16 A.10.2 Program Control Register A program control register is provided for EPROM programming. Address: Read: Write: Reset: $000D Bit 7 R 0 R 6 R 0 = Reserved 5 R 0 4 R 0 3 R 0 2 R 0 1 ELAT 0 Bit 0 PGM 0 Figure A-5. Program Control Register (PCR) Bits 7-3 -- Reserved These bits are reserved and read as logic 0 in user mode. Bit 2 -- Reserved This bit is not used and always reads as logic 0. ELAT -- EPROM LATch control 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming (Writes to EPROM cause address and data to be latched.) EPROM is in programming mode and cannot be read if ELAT is logic 1. This bit should not be set when no programming voltage is applied to the VPP pin. PGM -- EPROM ProGraM command 0 = Programming power switched off from EPROM array 1 = Programming power switched on to EPROM array If ELAT 1, then PGM = 0. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 138 Freescale Semiconductor LCD 1/2 Duty and 1/2 Bias Timing Diagram A.11 LCD 1/2 Duty and 1/2 Bias Timing Diagram DUTY = 1/2 BIAS = 1/2 (VLCD1 = VLCD2 = VDD-VLCD/2, VLCD3 = VDD-VLCD) 1FRAME BP0 VDD VLCD1, 2 VLCD3 VDD VLCD1, 2 VLCD3 VDD VLCD1, 2 VLCD3 VDD VLCD1, 2 VLCD3 +VLCD +VLCD/2 0 -VLCD/2 -VLCD +VLCD BP1-FPx (ON) +VLCD/2 0 -VLCD/2 -VLCD +VLCD +VLCD/2 0 -VLCD/2 -VLCD +VLCD +VLCD/2 0 -VLCD/2 -VLCD BP1 FPx (XX10) FPy (XX00) BP0-FPx (OFF) BP0-FPy (OFF) BP1-FPy (OFF) Figure A-6. CD 1/2 Duty and 1/2 Bias Timing Diagram MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 139 MC68HC705L16 A.12 Electrical Specifications This section contains parametric and timing information for the MC68HC705L16. A.12.1 Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. Keep VIn and VOut within the range VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. Rating Symbol VDD VLCD1 VLCD2 VLCD3 VIn VIn VOut I TJ Tstg Value -0.3 to +7.0 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD + 0.3 VSS -0.3 to 2 x VDD + 0.3 VSS -0.3 to VDD + 0.3 12.5 +150 -55 to +150 Unit Supply voltage V Input voltage Bootstrap mode (IRQ1 pin only) Output voltage Current drain per pin excluding VDD and VSS Operating junction temperature Storage temperature range V V V mA C C NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to A.13.2 5.0-Volt DC Electrical Characteristics and A.13.3 3.3-Volt DC Electrical Characteristics for guaranteed operating conditions. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 140 Freescale Semiconductor Recommended Operating Conditions A.12.2 Operating Temperature Range Characteristic Operating temperature range MC68HC705L16 (standard) MC68HC705L16C (extended) Symbol TA Value TL to TH 0 to +70 -40 to +85 Unit C A.12.3 Thermal Characteristics Characteristic Thermal resistance 80-pin plastic quad flat pack Symbol JA Value 120 Unit C/W A.13 Recommended Operating Conditions Rating(1) (fOP = 2.1 MHz) (fOP = 1.0 MHz) Supply voltage Symbol VDD VDD VLCD1 VLCD2 VLCD3 Fast clock oscillation frequency External capacitance (fOSC = 3.52 MHz) Slow clock oscillation frequency External capacitance (fXOSC = 32.768 kHz) fOSC C1 C2 fXOSC CX1 CX2 -- -- -- -- -- -- Min 4.5 3.0 Typ 5.0 -- VDD - 1/3 VLCD VDD - 2/3 VLCD VDD - 3/3 VLCD 3.52 33 33 32.768 18 22 4.2 -- -- -- -- -- Max 5.5 5.5 Unit V V V V V MHz pF MHz pF 1. +3.0 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted A.13.1 EPROM Programming Voltage Characteristics(1) EPROM programming voltage 1. VDD = 5.0 Vdc, VSS = 0 Vdc, TA = 25 oC Symbol VPP Min 12.0 Typ 12.5 Max 13.0 Unit V MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 141 MC68HC705L16 A.13.2 5.0-Volt DC Electrical Characteristics Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 5.0 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Output low voltage (VDD = 5.0 V) (ILoad = 0.8 mA) PA0-PA7, PC0-PC7, PD1-PD7, PE0-PE7 Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fOP = 2.1 MHz) Wait (fOP = 2.1 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 5.0 V, TA = +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 5.0 V) PA0-PA7 PB0-PB7 PC0-PC7 LCD pin output impedance FP0-FP26 BP0-BP3 Symbol VOL VOH VOH VOL VIH VIL Min -- VDD -0.1 VDD -0.8 -- 0.8 x VDD VSS Typ Max Unit -- -- -- 0.1 -- -- V V -- -- -- 0.4 VDD 0.2 x VDD V V V IDD -- -- -- -- 6.0 3.0 3.0 17.0 -- 12.0 6.0 10.0 -- 1.0 mA mA A A A IIn -- IIn 40 40 160 -- -- 150 150 500 10 5 340 340 1000 20 18 A A A k k Zo, FP Zo, BP 1. +4.5 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 4.2 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, atop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current measured with output transistor turned off and VIn = 0 V. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 142 Freescale Semiconductor Recommended Operating Conditions A.13.3 3.3-Volt DC Electrical Characteristics Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 3.5 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Output low voltage (VDD = 3.5 V) (ILoad = 0.8 mA) PA0-PA7, PC0-PC7, PD1-PD7, PE0-PE7 Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fOP = 1.0 MHz) Wait (fOP = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 3.0 V, TA= +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 3.3 V) PA0-PA7 PB0-PB7 PC0-PC7 LCD pin output impedance FP0-FP26 BP0-BP3 Symbol VOL VOH VOH VOL VIH VIL Min -- VDD -0.1 VDD -0.8 -- 0.8 x VDD VSS Typ Max Unit -- -- -- 0.1 -- -- V V -- -- -- 0.4 VDD 0.2 x VDD V V V IDD -- -- -- -- 1.8 0.8 2.0 8.0 -- 8.0 5.0 10.0 -- 1.0 mA mA A A A IIn -- IIn 20 20 60 -- -- 80 80 300 10 5 230 230 760 20 18 A A A k k Zo, FP Zo, BP 1. +3.0 VDD < +4.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current measured with output transistor turned off and VIn = 0 V. MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 143 MC68HC705L16 A.13.4 3.3-Volt and 5.0-Volt Control Timing Characteristic(1) Frequency of oscillation (OSC) Crystal External clock Internal operating frequency(2), crystal or external clock (fOSC/2) VDD = 4.5 V to 5.5 V VDD = 3.0 V to 5.5 V Cycle time (fast OSC selected) VDD = 4.5 V to 5.5 V VDD = 3.0 V to 5.5 V RESET pulse width (when bus clock active) Timer Resolution Input capture (TCAP) pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period(3) OSC1 pulse width (external clock input) Symbol fOSC Min -- dc Max 4.2 4.2 Unit MHz fOP -- -- 2.1 1.0 MHz tcyc tRL tRESL tTH, tTL tILIH tILIL tOH, tOL 480 1.0 1.5 4.0 284 284 see note 110 -- -- -- -- -- -- -- -- ns s tcyc tcyc ns ns tcyc ns 1. +3.0 VDD +5.5 Vdc, VSS = 0 Vdc,TL TA TH, unless otherwise noted. 2. The system clock divider configuration (SYS1-SYS0 bits) should be selected such that the internal operating frequency (fOP) does not exceed value specified in fOP for a given fOSC. 3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc. A.14 MC Order Numbers Table A-4 shows the MC order numbers for the available package types. Table A-4. MC Order Numbers Package Type Operating Temperature Range 0C to +70C 80-pin plastic quad flat pack (QFP) -40C to +85C MC68HC705L16CFU MC Order Number MC68HC705L16FU MC68HC05L16 * MC68HC705L16 Data Sheet, Rev. 4.1 144 Freescale Semiconductor blank How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. MC68HC05L16 Rev. 4.1, 9/2005 |
Price & Availability of MC68HC705L16
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |